#159 shorter VEX encodings for certain reg-to-reg VMOVs

[nasm64developer]

http://sourceware.org/ml/binutils/2008-12/msg00246.html

VMOVQ, VMOVDQ[AU], and VMOV[SS|SD|[AU]PS|[AU]PD] have
two possible encodings for the reg-to-reg form.

Using a REX register can result in a 3-byte VEX, while
the alternate encoding would give a 2-byte VEX i.e. a
shorter encoding, which may be preferred.

(I preferred a suppressible warning over the automatic
selection of the alternate encoding.)

[nasm64developer]

changes

[nasm64developer]

sample code

[nasm64developer]

File Added: alt_vex2.asm

[nasm64developer]

sample list file

[nasm64developer]

File Added: alt_vex2.lst

[H. Peter Anvin]

We always use the C5 form if it is available. If this isn't working, it's a bug, and please file a report as such. As for the new project of supporting all alternate encodings, as always, patches are accepted.

[H. Peter Anvin]

The current version already implements this feature.

[H. Peter Anvin]

Nevermind - the issue is as follows: some operations have symmetric input operands, and can only use the C5 form for one of the possible variants.

[H. Peter Anvin]

The solution is simply to add swapped instruction variants to insns.dat after the official ones. The assembler should automatically pick up the relevant versions.