#559 AVX512 instructions with {sae} but no rounding control should specify vector size in LL bits

[A Fog]

AVX512 instructions that have the {sae} attribute set but cannot have a rounding mode attribute are coded by NASM (2.11.06) with the LL bits = binary 00. The LL bits should probably be = binary 10 to specify 512 bit vector length. See "Intel Architecture Instruction Set Extensions Programming Reference" 319433-022 OCTOBER 2014 table 4-7 and note 2 to table 4-12. On the other hand, the manual has no examples of instructions that allow {sae} for more than the highest vector length.
Examples:
vrangeps zmm1, zmm2, zmm3, {sae}, 04H
vcmpneqpd zmm1, zmm2, zmm3, {sae}
These instructions are coded with LL = 00. They probably should have LL = 10