Section B.2.5 of the NASM manual includes the following sentence:
\\If mod is 0, r/m is 4 (meaning the SIB byte is present) and base is 4, the effective address encoded is not [EBP+index] as the above rules would suggest, but instead [disp32+index]: the displacement field is present and is four bytes long, and there is no base register (but the index register is still processed in the normal way).//
The second "4" should be a "5".
Reference: page 361 of http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf
Poster: Alistair Turnbull (sf at minworks.co.uk).
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