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[myhdl-list] Lists of signals now do appear in vcd file

[Frederik T. <sp...@ne...>]

Hello everybody,

I just had a look into _traceSignals.py . I wrote a few lines to write
flattened memories into the vcd file. The vcd standard does not support
multidimensional arrays. You can see it in the attached screenshot.

If you have a signal like

ram = [Signal(intbv(0, max=LMAX, min=-LMAX)) for i in range(N)]

the list items now appear as ram(0), ram(1), .. , ram(N-1) in the vcd file.

I attached a patch and the patched files, too.

It would be nice if you could test this code on your designs. If there
might be any problems or there are any please report them to me.

This patch announces a new trace option called
"traceSignalsAndMemories". If you use "traceSignals" no memories are dumped.

Example:

# The normal trace
tb = traceSignals(testBenchDut)
sim = Simulation(tb)
sim.run()

# can be changed to
tb = traceSignalsAndMemories(testBenchDut)
sim = Simulation(tb)
sim.run()
# .. to trace the memories as well.

It works with both the stable 0.7-version and the version from the
repository.


Happy debugging,

Frederik


Am 28.03.2012 15:08, schrieb Oscar Diaz:
> 2012/3/28 Frederik T. <sp...@ne...>:
>> Hello Oscar,
>>
>> that sounds great. I would test it, if it would help you.
> 
> This is a "very" preliminary version of signal_monitor, a class to
> generate vcd files in myhdl. As you can guess, it has little
> documentation (sorry for that) and probably needs a lot of adjustments
> and improvements. Feel free to test it and send me any suggestions,
> doubts or even complains about it. I'll try to finish it ASAP and
> upload in the myhdl wiki (or somewhere else if needed).
> 
> I hope this helps you or anyone on the mail list.
> 
> Best regards
> 
>>
>>
>> Regards,
>>
>> Frederik
>>
>> Am 28.03.2012 13:28, schrieb Oscar Diaz:
>>> 2012/3/27 Christopher Felton <chr...@gm...>:
>>>> On 3/27/2012 9:43 AM, Frederik T. wrote:
>>>>> Hello everybody,
>>>>>
>>>>> I have a question concerning lists of signals. Whenever I use a list of
>>>>> signals I don't see they don't appear in the vcd file created by
>>>>> traceSignals(), see gtkwave.png .
>>>>>
>>>>
>>>> That is correct, currently a "List of Signals" is not traced with
>>>> traceSignals.
>>>
>>> I had this problem a couple months ago, and I make a custom vcd
>>> generator that adds manually the signals that you need, assuming you
>>> had the references to the desired signals (and it supports lists and
>>> dicts of signals). The main idea is to make an object that returns
>>> generators that react to traced signals and generate the vcd file. It
>>> is completely unrelated to traceSignals function.
>>>
>>> It works for my needs but I'm afraid it needs refactoring. I can send
>>> my code if you need it, anyway I'm planning to fix it, upload
>>> somewhere and receive feedback on the list.
>>>
>>> As soon I fix it I'll announce it on the list.
>>>
>>>>
>>>> Regards,
>>>> Chris
>>>>
>>>>
>>>> ------------------------------------------------------------------------------
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>>>
>>> Best regards
>>>
>>
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> 
> 
> 
> 
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Re: [myhdl-list] Lists of signals don't appear in vcd file

[Oscar D. <osc...@gm...>]

2012/3/28 Frederik T. <sp...@ne...>:
> Hello Oscar,
>
> that sounds great. I would test it, if it would help you.

This is a "very" preliminary version of signal_monitor, a class to
generate vcd files in myhdl. As you can guess, it has little
documentation (sorry for that) and probably needs a lot of adjustments
and improvements. Feel free to test it and send me any suggestions,
doubts or even complains about it. I'll try to finish it ASAP and
upload in the myhdl wiki (or somewhere else if needed).

I hope this helps you or anyone on the mail list.

Best regards

>
>
> Regards,
>
> Frederik
>
> Am 28.03.2012 13:28, schrieb Oscar Diaz:
>> 2012/3/27 Christopher Felton <chr...@gm...>:
>>> On 3/27/2012 9:43 AM, Frederik T. wrote:
>>>> Hello everybody,
>>>>
>>>> I have a question concerning lists of signals. Whenever I use a list of
>>>> signals I don't see they don't appear in the vcd file created by
>>>> traceSignals(), see gtkwave.png .
>>>>
>>>
>>> That is correct, currently a "List of Signals" is not traced with
>>> traceSignals.
>>
>> I had this problem a couple months ago, and I make a custom vcd
>> generator that adds manually the signals that you need, assuming you
>> had the references to the desired signals (and it supports lists and
>> dicts of signals). The main idea is to make an object that returns
>> generators that react to traced signals and generate the vcd file. It
>> is completely unrelated to traceSignals function.
>>
>> It works for my needs but I'm afraid it needs refactoring. I can send
>> my code if you need it, anyway I'm planning to fix it, upload
>> somewhere and receive feedback on the list.
>>
>> As soon I fix it I'll announce it on the list.
>>
>>>
>>> Regards,
>>> Chris
>>>
>>>
>>> ------------------------------------------------------------------------------
>>> This SF email is sponsosred by:
>>> Try Windows Azure free for 90 days Click Here
>>> http://p.sf.net/sfu/sfd2d-msazure
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>>
>> Best regards
>>
>
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Re: [myhdl-list] Lists of signals don't appear in vcd file

[Frederik T. <sp...@ne...>]

Hello Oscar,

that sounds great. I would test it, if it would help you.


Regards,

Frederik

Am 28.03.2012 13:28, schrieb Oscar Diaz:
> 2012/3/27 Christopher Felton <chr...@gm...>:
>> On 3/27/2012 9:43 AM, Frederik T. wrote:
>>> Hello everybody,
>>>
>>> I have a question concerning lists of signals. Whenever I use a list of
>>> signals I don't see they don't appear in the vcd file created by
>>> traceSignals(), see gtkwave.png .
>>>
>>
>> That is correct, currently a "List of Signals" is not traced with
>> traceSignals.
> 
> I had this problem a couple months ago, and I make a custom vcd
> generator that adds manually the signals that you need, assuming you
> had the references to the desired signals (and it supports lists and
> dicts of signals). The main idea is to make an object that returns
> generators that react to traced signals and generate the vcd file. It
> is completely unrelated to traceSignals function.
> 
> It works for my needs but I'm afraid it needs refactoring. I can send
> my code if you need it, anyway I'm planning to fix it, upload
> somewhere and receive feedback on the list.
> 
> As soon I fix it I'll announce it on the list.
> 
>>
>> Regards,
>> Chris
>>
>>
>> ------------------------------------------------------------------------------
>> This SF email is sponsosred by:
>> Try Windows Azure free for 90 days Click Here
>> http://p.sf.net/sfu/sfd2d-msazure
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
> 
> Best regards
> 

Re: [myhdl-list] Lists of signals don't appear in vcd file

[Oscar D. <osc...@gm...>]

2012/3/27 Christopher Felton <chr...@gm...>:
> On 3/27/2012 9:43 AM, Frederik T. wrote:
>> Hello everybody,
>>
>> I have a question concerning lists of signals. Whenever I use a list of
>> signals I don't see they don't appear in the vcd file created by
>> traceSignals(), see gtkwave.png .
>>
>
> That is correct, currently a "List of Signals" is not traced with
> traceSignals.

I had this problem a couple months ago, and I make a custom vcd
generator that adds manually the signals that you need, assuming you
had the references to the desired signals (and it supports lists and
dicts of signals). The main idea is to make an object that returns
generators that react to traced signals and generate the vcd file. It
is completely unrelated to traceSignals function.

It works for my needs but I'm afraid it needs refactoring. I can send
my code if you need it, anyway I'm planning to fix it, upload
somewhere and receive feedback on the list.

As soon I fix it I'll announce it on the list.

>
> Regards,
> Chris
>
>
> ------------------------------------------------------------------------------
> This SF email is sponsosred by:
> Try Windows Azure free for 90 days Click Here
> http://p.sf.net/sfu/sfd2d-msazure
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Best regards

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Re: [myhdl-list] Describing a rom for Altera Quartus

[Norbo <Nor...@gm...>]

Just to share my insights on this topic:
I actually have never seen a altera FPGA with have dedicated ROM Blocks
inside.
Altera FPGAs are usually built out of LUT4 Blocks, some Registers, and
some dedicated memory or RAM Blocks (they need a positive clockege to
output data).
So am not quite sure what this (attribute romstyle : string;  attribute
romstyle of q : signal is "M9K";) does?

So my understanding on how quartus normaly maps is:

    * Rom with asynchron output
	-->  This is put on the FPGA into LUT4 Blocks
	     (this shows up as normal logic (combinatorical functions) synthesis
report)
    * Rom with sycnhron output (output is valid after the positive clk edge)
	--> This is put on the FPGA into the dedicated memory or RAM Blocks
(where the write logic is not used and they are pre
                initialized by the rom content)
    * RAM with asynchron output
	--> This is put on the FPGA into LUT4 Blocks and registers (because the
memory blocks need the clkedge for the output)
    * RAM with synchron output
           --> This is put on the FPGA into the dedicated memory or RAM
Blocks

And my understanding on how to write this down in myhdl so that quartus/
inferece the appropriate logic:

    * Rom with asynchron output:
       (example from the manual)
       ----------------------------------------
       from myhdl import *
       def rom(dout, addr, CONTENT):

	@always_comb
	def read():
	    dout.next = CONTENT[int(addr)]

	return read
       ----------------------------------------


    * Rom with sycnhron output: (output is valid after the positive clk  
edge)
       ----------------------------------------
       from myhdl import *
       def rom(clk,dout, addr, CONTENT):

	@always(clk.posedge)
	def read():
	    dout.next = CONTENT[int(addr)]

	return read
       ----------------------------------------


    * RAM with asynchron output_ (without initialisation of the memory)
       (example from the manual)
       ----------------------------------------
       from myhdl import *
       def RAM(dout, din, addr, we, clk, depth=128):
	""" Ram model """
	mem = [Signal(intbv(0)[8:]) for i in range(depth)]
	
	@always(clk.posedge)
	def write():
	    if we:
		mem[addr].next = din
	
	@always_comb
	def read():
	    dout.next = mem[addr]
	
	return write, read
        ----------------------------------------

    * RAM with synchron output (without initialisation of the memory):
       ----------------------------------------
       from myhdl import *
       def RAM(dout, din, addr, we, clk, depth=128):
	""" Ram model """
	mem = [Signal(intbv(0)[8:]) for i in range(depth)]
	
	@always(clk.posedge)
	def write_read():
	    if we:
		mem[addr].next = din
	    dout.next = mem[addr]
	
	return write_read
        ----------------------------------------

    * RAM with asynchron output (with pre-initialisation of the memory
content):
        Dont know a way to describe this in myhdl (i think the list of  
signal
would need to be initializable) then it could work.
       	
    * RAM with synchron output (with pre-initialisation of the memory
content):
        Dont know a way to describe this in myhdl


greetings
norbo


Am 28.03.2012, 10:56 Uhr, schrieb Frederik T. <sp...@ne...>:

> Hello Chris,
>
> I just tried it without success. Without the extra attributes the rom
> was made off logic elements. After I added them to the VHDL code
> everything was okay.
>
> Do you have another idea?
>
>
> Regards,
>
> Frederik
>
> Am 27.03.2012 20:32, schrieb Christopher Felton:
>> On 3/27/2012 11:18 AM, Frederik T. wrote:
>>> This is the template I found in Quartus II to describe a single port  
>>> rom:
>> <snip>
>>> begin
>>>
>>> 	process(clk)
>>> 	begin
>>> 	if(rising_edge(clk)) then
>>> 		q<= rom(addr);
>>> 	end if;
>>> 	end process;
>>>
>>> end rtl;
>>>
>>> It looks different then the case-when statements.
>>> Maybe I should generate VHDL code based on this template.
>>>
>>>
>>> Regards,
>>>
>>> Frederik
>>>
>>
>> I haven't tested/tried.  You should be able to use the "clocked"
>> generator in your MyHDL code for the read port and get similar generated
>> VHDL that Quartus should recognize as a ROM.  Instead of the always_comb
>> in the read port use a always(clk.posedge).
>>
>> Hope that helps,
>> Chris
>>
>>
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>
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[myhdl-list] Memory hungry and slow ram

[Frederik T. <sp...@ne...>]

Hello all,

I made a synchronous dual port ram with a single write port.

def dual_port_ram(clk, addr_a, addr_b, we_a, data_a, q_a, q_b,
datawidth, addrwidth):
    '''
        clk -- clock
        addr_a, addr_b -- addresses a, b
        data_a -- input data
        we_a -- write enable
        q_a, q_b -- output a, b
        datawidth -- width of data
        addrwidth -- bitwidth of addr

        A dual port ram with a single write port
    '''

    LMAX = 2**(datawidth-1)

    ram = [Signal(intbv(0, max=LMAX, min=-LMAX)) for i in
range(2**addrwidth)]

    @always(clk.posedge)
    def ports():
        if we_a:
            ram[addr_a].next = data_a

        q_a.next = ram[addr_a]
        q_b.next = ram[addr_b]

    return ports

It works in Xilinx ISE and Altera Quartus without any problems.

I realized that this design becomes really slow, if addrwidth rises.
This ram is used in a bit reverser component for an FFT processor. This
FFT than needs 3N Signals to hold all the data needed, where N is the
number of FFT points.

I tried to simulate an FFT with N=65536 it was really slow and took
about 30 minutes on a modern machine. The simulation lasts three FFT
frames. So simulation N samples takes about 10 minutes.

After that I tried to simulate the next FFT size N=131072 and I had to
abort because it took more that 16 gigabytes of ram.

So it is impossible to even produce the VHDL-Code for an FFT greater
than 65536 with my computer, because this problem appears then using
toVHDL() or toVerilog(), too.

I think the problem is the great number of Signal()s of intbv()s that
are needed in this design.

Is there another way to describe a synchronous dual port ram that
doesn't need that much memory or can I speed it up another way? Using
another interpreter like pypy or so?

Or is there a way to have a signal-list instead of a list of signals?

Thanks in advance


Regards,

Frederik

Re: [myhdl-list] Describing a rom for Altera Quartus

[Frederik T. <sp...@ne...>]

Hi Chris,

it works now. I accidently put a reset_n into my ports which is not
needed at all - this is clear. That was a problem when I tried the
clocked variant. A classical copy paste error.

Thanks for your help.

I found

http://www.altera.com/literature/hb/qts/qts_qii51007.pdf

Example 11–3 is exactly what I needed to know.

I can conclude that describing a rom needs a clock input to be
synthesizable in quartus.

My code is now:

def twiddlerom(clk, addr, doutr, douti, N, bitwidth):
    '''
        A rom that holds twiddle factors for a FFT
        addr -- address
        doutr, douti -- data out, real and imaginary
        N -- Number of twiddles
    '''

    LMAX = 2**(bitwidth-1)
    MMAX = 2**(2*bitwidth)

    def getTwiddles(N):
        # ...
        return tuple(ret)


    tmpcontent = getTwiddles(N)
    ram = tmpcontent

    tmp = Signal(intbv(0, min=-MMAX, max=MMAX)[2*bitwidth:])

    #@always_comb # doesn't work in quartus
    #def read():
    #    tmp.next = ram[int(addr)]

    @always(clk.posedge)
    def read():
        tmp.next = ram[int(addr)]

    @always_comb
    def devide():
        doutr.next = tmp[2*bitwidth:bitwidth].signed()
        douti.next = tmp[bitwidth:0].signed()

    return read, devide


Kind regards from Germany,

Frederik

Re: [myhdl-list] Describing a rom for Altera Quartus

[Frederik T. <sp...@ne...>]

Hello Chris,

I just tried it without success. Without the extra attributes the rom
was made off logic elements. After I added them to the VHDL code
everything was okay.

Do you have another idea?


Regards,

Frederik

Am 27.03.2012 20:32, schrieb Christopher Felton:
> On 3/27/2012 11:18 AM, Frederik T. wrote:
>> This is the template I found in Quartus II to describe a single port rom:
> <snip>
>> begin
>>
>> 	process(clk)
>> 	begin
>> 	if(rising_edge(clk)) then
>> 		q<= rom(addr);
>> 	end if;
>> 	end process;
>>
>> end rtl;
>>
>> It looks different then the case-when statements.
>> Maybe I should generate VHDL code based on this template.
>>
>>
>> Regards,
>>
>> Frederik
>>
> 
> I haven't tested/tried.  You should be able to use the "clocked" 
> generator in your MyHDL code for the read port and get similar generated 
> VHDL that Quartus should recognize as a ROM.  Instead of the always_comb 
> in the read port use a always(clk.posedge).
> 
> Hope that helps,
> Chris
> 
> 
> ------------------------------------------------------------------------------
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Re: [myhdl-list] initial blocks in Verilog

[Christopher F. <chr...@gm...>]

On 3/23/2012 5:21 AM, John Sager wrote:
> I note this as an open task. It bit me trying to co-simulate code in Icarus.
> Essentially the presence of 'undefined' states at the beginning of a simulation
> can give incorrect results. For example an integrator may have its register
> initialised by a reset in the logic, but in simulation, if it receives an
> 'undefined' input, that will propagate into the register and never change
> thereafter! In real logic, depending on circumstance, it may not be necessary to
> reset everything and incur the logic overhead to do that. Undefined (or
> actually, defined by switch-on transients but unknown) states in a pipeline, for
> example, will flush out eventually.
>
> I've added a simple function to _toVerilog.py, modelled on _writeSigDecls, which
> initialises variables in the siglist to the stored value, and initialises RAM in
> memlist to zero with a for loop. Signals of enums are set to zero, as there is
> no obvious initial value for them. Code including initial blocks generated by
> this addition has compiled successfully in Altera's Quartus II web edition.
>
> The open task description talks about dealing with lists of signals and intbvs.
> I'm not sure what else is required to do that though, so this addition may need
> more work.
>

Thanks for the post John,

Not sure if you simply wanted to share some changes that you have made 
or if you want to provide a patch for a future release.  If the later is 
the case you will want to review the following,

http://www.myhdl.org/doku.php/dev:patches

For this task is sounds like you tested the main open item, Quartus 
support of initialized values.  To address close this issue the 
following would need to be completed:

   * VHDL initial value and Verilog.
   * testing other synthesis (others probably can assist).
   * test cases to include in the unit testing.

Regards,
Chris

Re: [myhdl-list] Describing a rom for Altera Quartus

[Christopher F. <chr...@gm...>]

On 3/27/2012 11:18 AM, Frederik T. wrote:
> This is the template I found in Quartus II to describe a single port rom:
<snip>
> begin
>
> 	process(clk)
> 	begin
> 	if(rising_edge(clk)) then
> 		q<= rom(addr);
> 	end if;
> 	end process;
>
> end rtl;
>
> It looks different then the case-when statements.
> Maybe I should generate VHDL code based on this template.
>
>
> Regards,
>
> Frederik
>

I haven't tested/tried.  You should be able to use the "clocked" 
generator in your MyHDL code for the read port and get similar generated 
VHDL that Quartus should recognize as a ROM.  Instead of the always_comb 
in the read port use a always(clk.posedge).

Hope that helps,
Chris

Re: [myhdl-list] Describing a rom for Altera Quartus

[Frederik T. <sp...@ne...>]

This is the template I found in Quartus II to describe a single port rom:

-- Quartus II VHDL Template
-- Single-Port ROM

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity single_port_rom is

	generic
	(
		DATA_WIDTH : natural := 8;
		ADDR_WIDTH : natural := 8
	);

	port
	(
		clk		: in std_logic;
		addr	: in natural range 0 to 2**ADDR_WIDTH - 1;
		q		: out std_logic_vector((DATA_WIDTH -1) downto 0)
	);

end entity;

architecture rtl of single_port_rom is

	-- Build a 2-D array type for the RoM
	subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
	type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;

	function init_rom
		return memory_t is
		variable tmp : memory_t := (others => (others => '0'));
	begin
		for addr_pos in 0 to 2**ADDR_WIDTH - 1 loop
			-- Initialize each address with the address itself
			tmp(addr_pos) := std_logic_vector(to_unsigned(addr_pos, DATA_WIDTH));
		end loop;
		return tmp;
	end init_rom;	

	-- Declare the ROM signal and specify a default value.	Quartus II
	-- will create a memory initialization file (.mif) based on the
	-- default value.
	signal rom : memory_t := init_rom;

begin

	process(clk)
	begin
	if(rising_edge(clk)) then
		q <= rom(addr);
	end if;
	end process;

end rtl;

It looks different then the case-when statements.
Maybe I should generate VHDL code based on this template.


Regards,

Frederik

Re: [myhdl-list] Describing a rom for Altera Quartus

[Frederik T. <sp...@ne...>]

Hallo Chris,

thanks for your answer. I just checked it but "Auto ROM Replacement" was
already "On".

Another idea?


Regards,

Frederik

Am 27.03.2012 18:09, schrieb Christopher Felton:
> 
>> attribute romstyle : string;
>> attribute romstyle of q : signal is "M9K";
>>
>> My questions are if there is a way to describe a rom that syntesizes in
>> Xilinx ISE and Altera Quartus without adding anything by hand (or code).
>>
> <snip.
> There are also synthesis switches for "auto ROM" extraction.  You might 
> want to check if these are set or not.
> 
> Regards,
> Chris
> 
> 
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Re: [myhdl-list] Describing a rom for Altera Quartus

[Christopher F. <chr...@gm...>]

> attribute romstyle : string;
> attribute romstyle of q : signal is "M9K";
>
> My questions are if there is a way to describe a rom that syntesizes in
> Xilinx ISE and Altera Quartus without adding anything by hand (or code).
>
<snip.
There are also synthesis switches for "auto ROM" extraction.  You might 
want to check if these are set or not.

Regards,
Chris

Re: [myhdl-list] Lists of signals don't appear in vcd file

[Christopher F. <chr...@gm...>]

On 3/27/2012 9:43 AM, Frederik T. wrote:
> Hello everybody,
>
> I have a question concerning lists of signals. Whenever I use a list of
> signals I don't see they don't appear in the vcd file created by
> traceSignals(), see gtkwave.png .
>

That is correct, currently a "List of Signals" is not traced with 
traceSignals.

Regards,
Chris

[myhdl-list] Describing a rom for Altera Quartus

[Frederik T. <sp...@ne...>]

Hello all together,

I have a problem with a rom that holds precalculated twiddle factors for
a r2²sdf-pipeline-fft.

I took the rom from the examples directory and changed it and changed it:

def twiddlerom(doutr, douti, addr, N, bitwidth):
    '''
        A rom that holds twiddle factors for a FFT
        doutr, douti-- data out, real and imaginary
        addr -- address
        N    -- Number of twiddles

        Append:
        attribute romstyle : string;
        attribute romstyle of tmp : signal is "M9K";
    '''

    LMAX = 2**(bitwidth-1)
    MMAX = 2**(2*bitwidth)

    def getTwiddles(N):
	ret = [ ... ]
        # ...
	
        return tuple(ret)


    tmpcontent = getTwiddles(N)
    ram = tmpcontent

    tmp = Signal(intbv(0, min=-MMAX, max=MMAX)[2*bitwidth:])

    @always_comb
    def read():
        tmp.next = ram[int(addr)]

    @always_comb
    def devide():
        doutr.next = tmp[2*bitwidth:bitwidth].signed()
        douti.next = tmp[bitwidth:0].signed()

    return read, devide

The rom holds complex twiddles that are devided in the devide generator.
If I just output single values the mentioned problem doesnt' disappear.

Simulation works and Xilinx ISE compiles it into a rom. But Quartus uses
logic blocks until I add the following lines into the generated VHDL code:

attribute romstyle : string;
attribute romstyle of q : signal is "M9K";

My questions are if there is a way to describe a rom that syntesizes in
Xilinx ISE and Altera Quartus without adding anything by hand (or code).

Or is there a way to add some lines into the code but not generate the
whole VHDL or Verilog code, e.g.

__vhdl__.addLine(\
"""attribute romstyle : string;
attribute romstyle of q : signal is "M9K";"""

?

If not this would be a great improment I think.


Kind regards

Frederik

[myhdl-list] Lists of signals don't appear in vcd file

[Frederik T. <sp...@ne...>]

Hello everybody,

I have a question concerning lists of signals. Whenever I use a list of
signals I don't see they don't appear in the vcd file created by
traceSignals(), see gtkwave.png .

An example:

def shiftregister(clk, reset_n, en, din, dout, N, bitwidth):
    '''
        clk     -- clock
        reset_n -- low active reset
        en      -- enable, high active
        din     -- data in
        div     -- data in valid
        dout    -- data out
        dov     -- data out valid
        N       -- number of registers
    '''

    LMAX = 2**(bitwidth-1)

    regs = [Signal(intbv(0, max=LMAX, min=-LMAX)) for ii in range(N)]

    @always(clk.posedge, reset_n.negedge)
    def rtl():
        if reset_n == 0:
            for ii in range(N):
                regs[ii].next = 0
        else:
            if en:
                for ii in range(N-1):
                    regs[ii+1].next = regs[ii]

                regs[0].next = din

    @always_comb
    def comb():
        dout.next = regs[N-1]

    return rtl, comb

>% >% >% >% >% >% >% >%

bitwidth = 16
N = 4

tb = traceSignals(testBenchshiftregister, N, bitwidth)
sim = Simulation(tb)
sim.run()

If I add the signals

reg1, reg2, reg3, reg4 = [Signal(intbv(0, max=LMAX, min=-LMAX)) for ii
in range(N)] # N is 4

the signals appear in the vcd file like in gtkwave2.png .

So what am I doing wrong? Using lists of signals is more generic than
the other way but obiously not debuggable.


Kind regards

Frederik

[myhdl-list] initial blocks in Verilog

[John S. <jo...@sa...>]

I note this as an open task. It bit me trying to co-simulate code in Icarus.
Essentially the presence of 'undefined' states at the beginning of a simulation
can give incorrect results. For example an integrator may have its register
initialised by a reset in the logic, but in simulation, if it receives an
'undefined' input, that will propagate into the register and never change
thereafter! In real logic, depending on circumstance, it may not be necessary to
reset everything and incur the logic overhead to do that. Undefined (or
actually, defined by switch-on transients but unknown) states in a pipeline, for
example, will flush out eventually.

I've added a simple function to _toVerilog.py, modelled on _writeSigDecls, which
initialises variables in the siglist to the stored value, and initialises RAM in
memlist to zero with a for loop. Signals of enums are set to zero, as there is
no obvious initial value for them. Code including initial blocks generated by
this addition has compiled successfully in Altera's Quartus II web edition.

The open task description talks about dealing with lists of signals and intbvs.
I'm not sure what else is required to do that though, so this addition may need
more work.

Here is a patch on _toVerilog.py to add this functionality:

--- myhdl/myhdl/conversion/_toVerilog.py	2012-03-23 09:42:06.000000000 +0000
+++ myhdl-0.8dev_jcs/myhdl/conversion/_toVerilog.py	2012-03-17
11:17:14.000000000 +0000
@@ -94,7 +94,8 @@
                  "radix",
                  "header",
                  "no_myhdl_header",
-                 "no_testbench"
+                 "no_testbench",
+		 "initial"
                  )
 
     def __init__(self):
@@ -106,6 +107,7 @@
         self.header = ''
         self.no_myhdl_header = False
         self.no_testbench = False
+	self.initial = False
 
     def __call__(self, func, *args, **kwargs):
         global _converting
@@ -148,6 +150,8 @@
         _writeFileHeader(vfile, vpath, self.timescale)
         _writeModuleHeader(vfile, intf, doc)
         _writeSigDecls(vfile, intf, siglist, memlist)
+	if self.initial:
+	  _writeSigInitial(vfile, intf, siglist, memlist)
         _convertGens(genlist, vfile)
         _writeModuleFooter(vfile)
 
@@ -297,6 +301,29 @@
             print >> f, s.toVerilog()
     print >> f
 
+def _writeSigInitial(f, intf, siglist, memlist):
+    if len(memlist) > 0:
+        print >> f, "integer kk;"
+    print >> f, "initial begin"
+    for s in siglist:
+        if not s._used:
+            continue
+#        if s._name in intf.argnames:
+#            continue
+	if s._driven and s._driven == 'reg':
+	    if isinstance(s._val, (bool,int,long,intbv)):
+	      v = s._val
+	    else:
+	      v = 0
+	    print >> f, "    %s = %d;" % (s._name, v)
+    for m in memlist:
+        if not m._used:
+	    continue
+	if m._driven and m._driven == 'reg':
+	    print >> f, "    for (kk=0;kk<%d;kk=kk+1)" % (m.depth)
+	    print >> f, "        %s[kk] = 0;" % (m.name)
+    print >>f, "end"
+    
 
 def _writeModuleFooter(f):
     print >> f, "endmodule"

Re: [myhdl-list] Migen logic design toolbox - now with simulator

[Norbo <Nor...@gm...>]

I Just created a very simple and draft myhdl Version of Migen:
But i think splitting combinatorical and seqential statments up and slice  
them into further smaller statments, doesnt really makes it easy to  
comprehend what is done in the code. But probably with the power of the  
human brain nearly anything is possible.


 from myhdl import *

   comb=[]
   sync=[]
   localSignals=[]
   resetValues=[]

   ######### signal definitioons for startup ############
   localSignals+=["adrs=Signal(intbv(0)[24:])"]
   resetValues+=["adrs.next=0"]


   ##### combinatorial statments #############
   comb+=["if sel==0: out.next=0"]
   comb+=["if sel==1: out.next=1"]
   comb+=["adr.next=adrs"]

   ##### synchronus statments #############
   sync+=["if en: adrs.next=adrs+1"]





   source_text="""def TOP(clk,rst,out,adr,sel,en):
   """+"\n ".join(localSignals)+"""
   @always_comb
   def comb_logic():
     """+"\n   ".join(comb)+"""

   @always(clk.posedge,rst.negedge)
   def seq_logic():
     if rst==0:
       """+"\n     ".join(resetValues)+"""
     else:
       """+"\n     ".join(sync)+"""

   return seq_logic,comb_logic"""

   source_file=open("sourcetext.txt","w")
   source_file.write(source_text)
   source_file.close()
   dd=compile(source_text,"sourcetext.txt","exec")
   exec(dd)

   def test_bench():
       clk=Signal(bool(0))
       rst=Signal(bool(0))
       out=Signal(intbv(0)[4:])
       adr=Signal(intbv(0)[24:])
       sel=Signal(bool(0))
       en=Signal(bool(0))
       instanc_top=TOP(clk,rst,out,adr,sel,en)
       #toVHDL(TOP,clk,out,sel,en)

       @always(delay(10))
       def clkgen():
	  clk.next = not clk


       @instance
       def stimulus():
	rst.next=0
	yield clk
	rst.next=1
	sel.next=0
	yield clk
	yield clk
	print "Value of Output is", out
	sel.next=1
	en.next=1
	yield clk
	yield clk
	print "Value of Output is", out
	for i in range(40):
	  yield clk
	  print "adr Value:", adr
	raise StopSimulation

       return  stimulus,clkgen,instanc_top


   if __name__ == '__main__':
       hello_inst = test_bench()
       sim = Simulation(hello_inst)
       sim.run()





 

Re: [myhdl-list] Migen logic design toolbox - now with simulator

[Jan D. <ja...@ja...>]

On 03/21/2012 10:51 AM, Sébastien Bourdeauducq wrote:
> On 03/21/2012 10:43 AM, Sébastien Bourdeauducq wrote:
>> comb += [If(a[i], pos.eq(i)) for i in downrange(a.bv.width)]
>
> Of course, it should be "range" here, not "downrange".

Apart from my other, more fundamental objections: no, not OK.

In a circuit that checks the MSB position I want to check
the MSB first, and set the position once by stopping as soon
as it is found.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

[myhdl-list] FAQ: Tri-states

[Christopher F. <chr...@gm...>]

A frequently asked question is how to implement a tri-state.  Tri-states 
are not commonly implemented in the main digital logic but can be used 
on external interfaces.  For more information, description, and 
background please review the following:

   [1] http://www.myhdl.org/doku.php/meps:mep-103
   [2] http://www.myhdl.org/doku.php/meps:mep-105
   [3] http://www.myhdl.org/doc/current/whatsnew/0.7.html#shadow-signals

I gave a shot at creating a tri-state example, everything generated as 
expected *BUT* for this example the bi-dir signal was not defined as an 
inout in the Verilog?  It was defined as an inout in the VHDL.

~~~~[Code Example]~~~~
from myhdl import *


def top(sda, scl, sda_i, sda_o, scl_i, scl_o):
     """Simple I2C bi-dir converter.
     This example will break the I2C bi-directional signals into
     uni-dir explicit signals.
     """
     sda_d = sda.driver()
     scl_d = scl.driver()

     @always_comb
     def hdl():
         sda_i.next = sda
         sda_d.next = False if not sda_o else None

         scl_i.next = scl
         scl_d.next = False if not scl_o else None

     return hdl


def convert():
     clk = Signal(False)
     rst = Signal(False)
     sda = TristateSignal(True)
     scl = TristateSignal(True)
     sda_i = Signal(False)
     sda_o = Signal(False)
     scl_i = Signal(False)
     scl_o = Signal(False)

     toVerilog(top, sda, scl, sda_i, sda_o, scl_i, scl_o)
     toVHDL(top, sda, scl, sda_i, sda_o, scl_i, scl_o)

if __name__ == '__main__':
     convert()

~~~~[End Code Example]~~~~

Regards,
Chris

Here are the converted files
~~~~[top.vhd]~~~~
-- File: top.vhd
-- Generated by MyHDL 0.8dev
-- Date: Wed Mar 21 08:25:04 2012


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_08dev.all;

entity top is
     port (
         sda: inout std_logic;
         scl: inout std_logic;
         sda_i: out std_logic;
         sda_o: in std_logic;
         scl_i: out std_logic;
         scl_o: in std_logic
     );
end entity top;
-- Simple I2C bi-dir converter.
-- This example will break the I2C bi-directional signals into
-- uni-dir explicit signals.  Useful for driving I2C buses.

architecture MyHDL of top is

signal scl_d: std_logic;
signal sda_d: std_logic;

begin


scl <= None;
scl <= scl_d;
sda <= None;
sda <= sda_d;



sda_i <= sda;
sda_d <= '0' when (not to_boolean(sda_o)) else to_std_logic((others => 
'Z'));
scl_i <= scl;
scl_d <= '0' when (not to_boolean(scl_o)) else to_std_logic((others => 
'Z'));

end architecture MyHDL;


~~~~[top.v]~~~~
// File: top.v
// Generated by MyHDL 0.8dev
// Date: Wed Mar 21 08:25:04 2012


`timescale 1ns/10ps

module top (
     sda,
     scl,
     sda_i,
     sda_o,
     scl_i,
     scl_o
);
// Simple I2C bi-dir converter.
// This example will break the I2C bi-directional signals into
// uni-dir explicit signals.  Useful for driving I2C buses.

output sda;
wire sda;
output scl;
wire scl;
output sda_i;
wire sda_i;
input sda_o;
output scl_i;
wire scl_i;
input scl_o;

wire scl_d;
wire sda_d;



assign scl = scl_d;
assign sda = sda_d;



assign sda_i = sda;
assign sda_d = (!sda_o) ? 1'b0 : 'bz;
assign scl_i = scl;
assign scl_d = (!scl_o) ? 1'b0 : 'bz;

endmodule

Re: [myhdl-list] Migen logic design toolbox - now with simulator

[Christopher F. <chr...@gm...>]

On 3/21/2012 6:35 AM, Sébastien Bourdeauducq wrote:
> On 03/21/2012 12:27 PM, Christopher Felton wrote:
>> Ah, your modus aperandi.  You give a hand waiving description without
>> the example code.  Putting the work on someone else to provide an example.
>
> Oh, sorry.
> https://github.com/milkymist/milkymist-ng/blob/master/milkymist/asmicon/bankmachine.py#L196
>

This is Python?  I have never seen Python if-elif-else code written that 
way.

Regards,
Chris

Re: [myhdl-list] Migen logic design toolbox - now with simulator

[Sébastien B. <seb...@mi...>]

On 03/21/2012 12:27 PM, Christopher Felton wrote:
> Ah, your modus aperandi.  You give a hand waiving description without
> the example code.  Putting the work on someone else to provide an example.

Oh, sorry.
https://github.com/milkymist/milkymist-ng/blob/master/milkymist/asmicon/bankmachine.py#L196

Re: [myhdl-list] Migen logic design toolbox - now with simulator

[Christopher F. <chr...@gm...>]

On 3/21/2012 4:43 AM, Sébastien Bourdeauducq wrote:
> Hi,
>
> On 03/19/2012 01:30 PM, Jan Decaluwe wrote:
>>> If you are talking about VHDL variables / blocking Verilog assignments
>>> that can be used to synthesize sequential code that "executes" in one
>>> cycle, then they are supported too (with the "variable" property of the
>>> Signal object).
>>
>> That is what I call "horrible". These things are confusing enough,
>> even in VHDL that makes a clear distinction between signals
>> and variables. MyHDL improves further on this by using a
>> dedicated, distinctive attribute assignment for Signal
>> assignment.
>
> Well, it's just a small detail, no need to break such a fuss about it.
> What would you propose then? replace the "variable" property simply with
> the use of a different assignment? or enforce that another assignment
> method is used when the "variable" property is set?

I am confused, why would you ask for guidance on a "small detail".

>
>> def MsbDetector(pos, a):
>>        """Return the bit position of the msb."""
>>
>>        @always_comb
>>        def logic():
>>            pos.next = 0
>>            for i in downrange(len(a)):
>>                if a[i] == 1:
>>                    pos.next = i
>>                    break
>>
>>        return logic
>
> (...)
>
>> How would this look like in Migen?
>
> comb += [If(a[i], pos.eq(i)) for i in downrange(a.bv.width)]
>
<snip>
>> So far for elegance
>
> One line :)

Is not elegant.

>
>> and parametrizability.
>
> In this example, it's just as parametrizable as yours. In general, Migen
> is more parametrizable than MyHDL. Let's have another simple example:
> how would you parametrize the number of wait states (removing them
> entirely when the parameter is 0) at different points of a FSM?

Ah, your modus aperandi.  You give a hand waiving description without 
the example code.  Putting the work on someone else to provide an example.

>
>> Well, no. Look at the test bench code versus Migen code and
>> note that the modeling paradigm is entirely different.
>> But in practice, today's high-level model that is part
>> of the verification environment becomes tomorrow's
>> synthesizable model and vice versa.
>
> Following the same logic, you could say that all hardware and software
> designs should be written using high level languages such as Python,
> Ruby or Lisp normally, and hope that one day some magical synthesizer
> will make them fast and optimized on FPGA, ASIC and CPU. Given that Lisp
> is still slow more than 50 years after its invention, let me have doubts
> about this position.
>
> Or you can be pragmatic and do things like Migen.
>

Practicality is your defense?  You are taking a huge leap from 
high-level model propagation to your "magical synthesizer", I believe 
you missed the point.

Regards,
Chris

Re: [myhdl-list] Migen logic design toolbox - now with simulator

[Sébastien B. <seb...@mi...>]

On 03/21/2012 12:23 PM, Jan Decaluwe wrote:
> Because I think you missed the break, didn't you?

Yes I did, see my next email.

> Of course,
> I can't tell for sure because who knows how you handle the
> statement order in that list.

Just like Verilog/VHDL - last statement sets the value.

Sébastien

Re: [myhdl-list] Migen logic design toolbox - now with simulator

[Jan D. <ja...@ja...>]

On 03/21/2012 10:43 AM, Sébastien Bourdeauducq wrote:
> Hi,
>
> On 03/19/2012 01:30 PM, Jan Decaluwe wrote:
>>> If you are talking about VHDL variables / blocking Verilog assignments
>>> that can be used to synthesize sequential code that "executes" in one
>>> cycle, then they are supported too (with the "variable" property of the
>>> Signal object).
>>
>> That is what I call "horrible". These things are confusing enough,
>> even in VHDL that makes a clear distinction between signals
>> and variables. MyHDL improves further on this by using a
>> dedicated, distinctive attribute assignment for Signal
>> assignment.
>
> Well, it's just a small detail, no need to break such a fuss about it.

Only someone with too much Verilog exposure could say that.

The confusion about this small detail (because of the way Verilog
handles it) is the single most important cause of why HDL-based
design doesn't live up to its potential. As you know, in Verilog,
procedural techniques are virtually banned from clocked processes,
for no good reason except the confusion about this "detail".

> What would you propose then? replace the "variable" property simply with
> the use of a different assignment? or enforce that another assignment
> method is used when the "variable" property is set?

If it's such a small detail, I don't see why you want to
take HDL design lessons from me.

>> def MsbDetector(pos, a):
>>        """Return the bit position of the msb."""
>>
>>        @always_comb
>>        def logic():
>>            pos.next = 0
>>            for i in downrange(len(a)):
>>                if a[i] == 1:
>>                    pos.next = i
>>                    break
>>
>>        return logic
>
> (...)
>
>> How would this look like in Migen?
>
> comb += [If(a[i], pos.eq(i)) for i in downrange(a.bv.width)]

Did you simulate this?

Because I think you missed the break, didn't you? Of course,
I can't tell for sure because who knows how you handle the
statement order in that list.

I will give a free language (*any* language) design tip then:
when the statement order matters, it should visually stand out.
Of course it should.

> Notes:
> 1. the default 0 is implicit (reset value of a combinatorial signal)
> 2. you can build the pos signal with the right size using bits_for:
> pos = Signal(BV(bits_for(a.bv.width-1)))
> 3. we should add len() support for signals, thanks for the reminder :)
> 4. you can either assume the synthesizer will automagically build an
> optimized structure (it doesn't always), or use a bit more control, as in:
> http://www.ohwr.org/projects/tdc-core/repository/revisions/master/entry/core/tdc_lbc.vhd
> It's VHDL, but you could do the same with Migen too.
>
>> So far for elegance
>
> One line :)

Execpt it doesn't work I think.

And since when are one-liners synonymous to elegance? Often
they are the opposite: obfuscation that leads to hard-to-catch
errors, as in this case.

>> and parametrizability.
>
> In this example, it's just as parametrizable as yours. In general, Migen
> is more parametrizable than MyHDL.

That must be true, for those who like to break up their design into
concurrent statements themselves. I prefer to leave that work
to a synthesis tool.

>  Let's have another simple example:
> how would you parametrize the number of wait states (removing them
> entirely when the parameter is 0) at different points of a FSM?

A wait state and a wait state counter with a variable end count.

>> Well, no. Look at the test bench code versus Migen code and
>> note that the modeling paradigm is entirely different.
>> But in practice, today's high-level model that is part
>> of the verification environment becomes tomorrow's
>> synthesizable model and vice versa.
>
> Following the same logic, you could say that all hardware and software
> designs should be written using high level languages such as Python,
> Ruby or Lisp normally, and hope that one day some magical synthesizer
> will make them fast and optimized on FPGA, ASIC and CPU. Given that Lisp
> is still slow more than 50 years after its invention, let me have doubts
> about this position.

I am not talking about the uncertain future either. I am talking
about models that are not initially intended for synthesis, and evolve
to that requirement later.

> Or you can be pragmatic and do things like Migen.
>
>> Very often, this even happens within the same project.
>
> Can you give some examples?

Virtually any telecom chip where the TX side is verified by
looping back the RX side and vice versa.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com