Re: [myhdl-list] IP core library

[Christopher F. <chr...@gm...>]

On 4/25/15 1:54 PM, Euripedes Rocha Filho wrote:
> Hi,
> I'm starting a small (actually no IP so far) library and wondering if
> someone has some suggestion on how to structure it.Â

This is great, more IP (cores) development the
better.  Using common Python package structure
is a good place to start.

There are various projects out there,
here are a couple that you can look at:

This is my small collection of "cores", I slowly
add to it as I have time ...
https://github.com/cfelton/minnesota

FPGA digital radio (SDR) using MyHDL:
https://github.com/testaco/whitebox

Keerthan's HDL toolbox:
https://github.com/jck/uhdl

>
> The repository (just started the package using cookiecutter)
> Â https://github.com/euripedesrocha/instar
>
> My idea is to use MyHDL as both simulation and hdl decription language,
> using verilog conversion to put the design under the regular FPGA work
> flow ( also I'll use Chistopher's myhdl_tools package in the build flow ).
>

Note, I have moved the FPGA flow from myhdl_tools
to gizflo (couple reasons why and I can explain
if interested)
https://github.com/cfelton/gizflo

> What I have in mind now is:
>
> There's any advantage in use a class packing the interface signals and a
> method with the hardware description, or use another structure?

This depends, in my opinion you don't want to go
class/object crazy :)  Creating clean interfaces
will help the code a ton.  I tend to keep my main
modules not part of a class but for models I include
many myhdl generators in a class.

>
> Any thoughts?

One of the things you should do early is how you
want to structure the tests.  I would suggest using
py.test and following some of their suggestions:
https://pytest.org/latest/goodpractises.html

Following a TDD flow would be an good idea but takes
some discipline.

Regards,
Chris