Re: [myhdl-list] A VHDL question about signal assignments and delta cycles?

[Christopher F. <chr...@gm...>]

<snip>
>
> Is this a delta cycle thing? Is it simulation specific? I'm not too
> concerned about it, but I'd like to understand the reason behind it.

I have not reviewed your inquiry in detail but
this might help answer your question:

http://www.sigasi.com/content/vhdls-crown-jewel

Regards,
Chris