Re: [myhdl-list] MEP 107 Initial support
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Re: [myhdl-list] MEP 107 Initial support
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From: David H. <da...@ad...> - 2013-12-03 13:52:59
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Yeah, the down-side is for some of my parameterizable IP (coded in MyHDL)
where **kwargs is a natural fit, I currently have to write out a silly
temporary .py file just for MyHDL to analyze to extract the top-level port
names.
So, being able to relax the restriction on **kwargs (in exchange for the
caller must .portmap prior to export), would hopefully eliminate this
ugliness.
(example IP blocks: an N-port arbiter for AXI4-S streams... Or a PCIe BAR
interface that auto-creates software input/output bits for hardware control
from an OS driver...)
On Tue, Dec 3, 2013 at 12:05 AM, Christopher Felton
<chr...@gm...>wrote:
> On 12/2/13 9:06 PM, David Holl wrote:
> > If you go this route with the dict, I'd encourage the use of an
> > OrderedDict, so that argument order may be preserved. Then the top
> > level restriction that prevents **kwargs can be relaxed because the top
> > function wouldn't need to be analyzed to get at the signal names.
>
> Other than complexity, is there is downside
> to analyzing the top function to get the signal
> names?
>
> Regards,
> Chris
>
> >
> > On Dec 2, 2013 6:12 PM, "Christopher Felton" <chr...@gm...
> > <mailto:chr...@gm...>> wrote:
> >
> > On 10/2/2013 2:45 PM, Keerthan jai.c wrote:
> > > toVerilog returns whatever would be returned if you called the
> > function
> > > directly, usually a tuple of generators. So, someone could
> > hypothetically
> > > have been passing the return value of toVerilog to a
> myhdl.Simulation
> > > object. Returning the portmap alongside the previous return value
> > would
> > > break their code.
> > >
> > > toVerilog.portmap seems reasonable.
> > >
> > >
> >
> > How about the /portmap/ is tied to the module
> > (the function being passed) instead of the toV*?
> >
> > Because of another request I was thinking - it
> > could be useful to define the "default" port
> > types in a /portmap/ function attribute.
> >
> > Couple benefits:
> >
> > Â Â 1. Top-level modules often are specific, there
> > Â Â Â Â is only one mapping that makes sense
> >
> > Â Â 2. removes the need to re-declare the port
> > Â Â Â Â (simulation and conversion)
> >
> > Example:
> >
> > Â Â Â def m_adder(a,b,c):
> > Â Â Â Â Â @always_comb
> > Â Â Â Â Â def rtl():
> > Â Â Â Â Â Â Â c.next = a + b
> > Â Â Â Â Â return rtl
> >
> > Â Â Â iot = intbv(0, min=-8, max=8)
> > Â Â Â m_adder.portmap = {"a":Signal(iot),
> > Â Â Â Â Â Â Â Â Â Â Â Â "b":Signal(iot),
> > Â Â Â Â Â Â Â Â Â Â Â Â "c":Signal(iot)}
> >
> > A /vportmap/ (or something similar) function attribute
> > could be used to contain the expanded names. Â The port
> > definitions would be tied to the top-level function.
> >
> > .chris
> >
> >
> >
> >
> >
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