Re: [myhdl-list] MEP - keep hierarchy in conversion

[Christopher F. <chr...@gm...>]

<snip>
>
> Here are a couple articles for your consideration:
> http://electronicdesign.com/products/fundamentals-floor-planning-complex-soc
> http://en.wikipedia.org/wiki/Floorplan_(microelectronics)
>

I don't think anyone is saying floorplanning is not
used, but rather debating different flows.  If you look
at one of Jan's ASIC's [1] in which the digital macro
was implemented with MyHDL, you can see obvious floor
planning.  Planning of the IO, SRAM, analog, and digital
(similar to the articles you referenced).

This is how our ASICs have been developed as well, with a
analog top-level view where the digital macros are stitched
in with the various components.  Floorplanning is definitely
part of the project, just not part of the HDL flow.

And if you look at your first reference, the digital macro
in the design - no floorplanning.  Only floorplanning from
the top-level main components (SRAM, XPM, MCU, and IO) [2]
See that lower right hand blob, that is a bunch of their
digital stuff, auto-routed.  And then a second blog used to
connect all the various pieces - auto-routed.

Regards,
Chris

[1] http://www.jandecaluwe.com/hdldesign/digmac.html
[2] 
http://electronicdesign.com/site-files/electronicdesign.com/files/archive/electronicdesign.com/content/content/73618/73618_fig02.jpg