Re: [myhdl-list] Converting std_logic_vector to signed and vice versa

[Thomas H. <th...@ct...>]

 >> entity DSP is
 >>      port (
 >>          clock: in std_logic;
 >>          x: in signed (15 downto 0);
 >>          y: in signed (15 downto 0);
 >>          amplitude: in signed (15 downto 0);
 >>          offset: in signed (15 downto 0);
 >>          xout: out signed (15 downto 0);
 >>          yout: out signed (15 downto 0)
 >>      );
 >> end entity DSP;


Am 07.01.2011 20:28, schrieb Kevin Stanton:
> The signed type is a subtype of std_logic_vector (see the ieee.numeric_std
> package). Assuming you can used a signed binary word throughout, there
> should be no need to convert to std_logic_vector, unless you need to do
> arithmetic elsewhere that is unsigned and you wish to convert it to unsigned
> format.

Kevin,

what does this mean?  If I create a VHDL instantiation template for the
DSP then xilinx ISE creates this component declaration:

	COMPONENT DSP
	PORT(
		clock : IN std_logic;
		x : IN std_logic_vector(15 downto 0);
		y : IN std_logic_vector(15 downto 0);
		amplitude : IN std_logic_vector(15 downto 0);
		offset : IN std_logic_vector(15 downto 0);
		xout : OUT std_logic_vector(15 downto 0);
		yout : OUT std_logic_vector(15 downto 0)
		);
	END COMPONENT;

I thought it is a bug that ISE generates std_logic_vector types instead
of signed; do you mean that this is ok?

Thomas