[myhdl-list] Development status update

[Jan D. <ja...@ja...>]

Hi all:

In the previous months, I have completed another industrial
project with MyHDL. As usual, I have made a number of
enhancements to MyHDL, driven by the project needs.

There is more than enough material for a new release, and
I will start to work towards that now. As usual, the main work
will be to bring the documentation in sync. I am working
on a What's New document first.

MyHDL has come to a point were the open-source simulators for
Verilog and VHDL are becoming a bottleneck, because they
are no longer being developed (cver), or because it's sometimes
not clear whether a discrepancy comes from MyHDL onversion, or
from the simulator. As an alternative, I have now been able
to run the unit tests (that don't depend on cosimuluation) with
the free Modelsim simulator packaged with the Altera suite
for Linux. This gives me much more confidence, and I hope
this option will remain available in the future.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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