[myhdl-list] How to give signals custom names in toVHDL

[Sigve T. <pu...@tj...>]

Hi,

I have a problem where different signals get the same name in VHDL
when using toVHDL, caused when using two instances with identical
names according to _makeName.

I see that in _analyze.py there is this construction:
    for n, s in sigdict.items():
        if s._name is not None:
            continue

Setting the s._name on a signal causes the signal to use the assigned
name, but the "continue" above stops generation of the signal
declaration. I guess that the this construction is used for something
else.

What is the appropriate method to give a signal a specific name?
Setting only a part of a signal name (prefix or postfix) would also be
ok.

The autogenerated signal names are not always very informative, but
the worst problem is the signal name collision resulting in defective
VHDL.

Sigve