Re: [myhdl-list] Error in user defined VHDL code should show line, and column for error, rather than & amp; amp; amp; quot; index& amp; amp; amp; quot;

[Angel E. <ang...@gm...>]

Jan Decaluwe <jan <at> jandecaluwe.com> writes:

> 
> Angel Ezquerra wrote:
> > Jan Decaluwe <jan <at> jandecaluwe.com> writes:
> >> Ok, what we could do is specify that the code for the
> >> new function attribute 'vhdl_code' is actually such a
> >> template, which would force you to help me debugging
> >> those 
> >>
> >> If that's OK, I'll put this change on top of the stack.
> >>
> >> Jan
> >>
> > 
> > OK! Let me know what the change is done! 
> 
> It's out.
> 

The simple tests that I've performed work fine!
This new syntax, while similar, it is also easier
to understand than the old method.

One comment that I have, and which is related to
this thread, is that if you make a mistake with
the name of one of the ports that you want to link
to your VHDL code, you get the following error:

  myhdl.ToVHDLError: in file dsp48e.py,
  function dsp48e starting on line 3:
  Error in user defined VHDL code:
  <type 'exceptions.KeyError'>: 'CLK'

(Note that I had to error message a bit to 
work around gmane's 80 character line length
restriction).

In this case I purposely tried to use a signal named 
"CLK" while the actual signal was named "clk".

The error message is the same that you would get
when using the old "__vhdl__" magic variable.
Fortunately, this seems to be the only error
that you could get when using templates, while
when using the old method you could also get
errors with the format of the format string, etc.

This error makes sense if you know what
MyHDL is doing in the background (which is to
interpolate a string using the namespace dictionary).
However, if you don't what MyHDL is doing
then I think that the error is quite cryptic.
It tells you that there is an error related 
to "CLK", but what is a "KeyError" and what 
does it have to do with anything?

Ideally it would be much better if MyHDL told you
that the unknown 'CLK' signal was used on the
user-defined code string.

Something else that I have noticed is that
MyHDL adds 5 empty lines between the "begin"
keyword of the architecture and the beginning
of the user-defined code. This is obviously a
very minor thing, but I don't know if this
was there before of if it has been introduced
by the new template-based code.

Cheers,

Angel