[myhdl-list] if-elif to case conversion

[Jian L. <jia...@go...>]

Hi Jan,

I found the conversion from if-elif-else to case doesn't work in 0.7dev
anymore,
and tried to fix it.
So far I got Verilog version work, but toVHDL still fails.
Maybe you can find a clue, why it doesn't work.
Attached is the changeset patch.

My model looks like this:

from myhdl import *

bitwise_op = enum('BW_AND', 'BW_ANDN', 'BW_OR', 'BW_XOR')

def TestUnit(o, a, b, op):
    @always_comb
    def bitwise():
        r = intbv(0)[8:]
        if op == bitwise_op.BW_AND:
            r[:] = a & b
        elif op == bitwise_op.BW_ANDN:
            r[:] = (~a) & b
        elif op == bitwise_op.BW_OR:
            r[:] = a | b
        elif op == bitwise_op.BW_XOR:
            r[:] = a ^ b
        o.next = r
    return instances()

if __name__ == '__main__':
    a, b, c = [Signal(intbv(0)[8:]) for i in range(3)]
    op = Signal(bitwise_op.BW_AND)
    toVHDL(TestUnit, c, a, b, op)

and the error message:

Traceback (most recent call last):
  File "test_enum.py", line 23, in <module>
    toVHDL(TestUnit, c, a, b, op)
  File "/home/daniel/Sources/myhdl/myhdl/conversion/_toVHDL.py", line 148,
in __call__
    _convertGens(genlist, siglist, vfile)
  File "/home/daniel/Sources/myhdl/myhdl/conversion/_toVHDL.py", line 334,
in _convertGens
    v.visit(tree)
  File "/usr/lib64/python2.6/ast.py", line 231, in visit
    return visitor(node)
  File "/home/daniel/Sources/myhdl/myhdl/conversion/_toVHDL.py", line 1672,
in visit_Module
    self.visit(stmt)
  File "/usr/lib64/python2.6/ast.py", line 231, in visit
    return visitor(node)
  File "/home/daniel/Sources/myhdl/myhdl/conversion/_toVHDL.py", line 2375,
in visit_FunctionDef
    self.visit_stmt(node.body)
  File "/home/daniel/Sources/myhdl/myhdl/conversion/_toVHDL.py", line 2069,
in visit_stmt
    self.visit(stmt)
  File "/usr/lib64/python2.6/ast.py", line 231, in visit
    return visitor(node)
  File "/home/daniel/Sources/myhdl/myhdl/conversion/_toVHDL.py", line 1540,
in visit_If
    self.mapToCase(node)
  File "/home/daniel/Sources/myhdl/myhdl/conversion/_toVHDL.py", line 1584,
in mapToCase
    self.visit_stmt(suite)
  File "/home/daniel/Sources/myhdl/myhdl/conversion/_toVHDL.py", line 2069,
in visit_stmt
    self.visit(stmt)
  File "/usr/lib64/python2.6/ast.py", line 231, in visit
    return visitor(node)
  File "/home/daniel/Sources/myhdl/myhdl/conversion/_toVHDL.py", line 993,
in visit_Assign
    if isinstance(lhs.vhd, vhd_type):
AttributeError: 'Subscript' object has no attribute 'vhd'

Cheers,

Jian