Re: [myhdl-list] Records in VHDL and MyHDL

[Jan D. <ja...@ja...>]

Sigve Tjora wrote:
> Hi!
> 
> I generate VHDL from MyHDL and when the design has some size, it becomes 
> tedious and error prone to connect all the signals. Is it possible to 
> generate VHDL that uses VHDL-records to group related signals together 
> in the port-list of the generated VHDL code?

Conversion hasn't support for something like this at this moment.

One problem is that I want a solution that works for both Verilog
and VHDL, as I want to address the whole audience. Therefore,
I am more thinking about something like interfaces, that then
would "disappear" in the converted output.

BTW, to avoid connection tediousness, I typically use another
solution currently. I give ports and signals at the highest
level of hierarchy unique names, and declare them in
separate modules. I then import them in the namespace,
and use a function that does name-based lookup to make
the connections automatically, based on the interface
of a module.

Jan

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