Re: [myhdl-list] Xilinx ISE and MyHDL

[Jan D. <ja...@ja...>]

Mike Gill wrote:
> Hi,
> 
> It is very attractive for the entire source code for a Xilinx ISE project to be 
> managed in Python via myHDL. This needs Xilinx chip features like clock 
> generators and RAM to be defined in Python. Is this possible, and what is the 
> best approach?

In many cases, RAMs can be inferred from technology-independent
RTL code, which is the preferred approach if it works.

To instantiate technology-specific modules, you can use the
__verilog__ or __vhdl__ hook. For simulation purposes,
describe the functionality as usual. The convertor
will ignore that code and use the appopriate hook if it exists.

See:

http://www.myhdl.org/doc/0.6/manual/conversion.html#user-defined-code

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
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