[Mspsim-commit] SF.net SVN: mspsim:[385] mspsim/se/sics/mspsim/chip/CC2420.java

[<jo...@us...>]

Revision: 385
          http://mspsim.svn.sourceforge.net/mspsim/?rev=385&view=rev
Author:   joxe
Date:     2008-10-28 16:11:39 +0000 (Tue, 28 Oct 2008)

Log Message:
-----------
added overflow state

Modified Paths:
--------------
    mspsim/se/sics/mspsim/chip/CC2420.java

Modified: mspsim/se/sics/mspsim/chip/CC2420.java
===================================================================
--- mspsim/se/sics/mspsim/chip/CC2420.java	2008-10-28 13:39:31 UTC (rev 384)
+++ mspsim/se/sics/mspsim/chip/CC2420.java	2008-10-28 16:11:39 UTC (rev 385)
@@ -340,6 +340,7 @@
   };
   private boolean currentSFD;
   private boolean currentFifo;
+  private boolean overflow = false;
 
   // TODO: super(cpu) and chip autoregister chips into the CPU.
   public CC2420(MSP430Core cpu) {
@@ -351,7 +352,7 @@
     fifoP = false;
     rxfifoReadPos = 0;
     rxfifoWritePos = 0;
-    
+    overflow = false;
     cpu.addChip(this);
   }
   
@@ -487,9 +488,9 @@
           // In RX mode, FIFOP goes high, if threshold is higher than frame length....
 
           // Should take a RSSI value as input or use a set-RSSI value...
-          memory[RAM_RXFIFO + (rxfifoWritePos - 2)] = (registers[REG_RSSI]) & 0xff;
+          memory[RAM_RXFIFO + ((rxfifoWritePos + 128 -2) & 127)] = (registers[REG_RSSI]) & 0xff;
           // Set CRC ok and add a correlation
-          memory[RAM_RXFIFO + (rxfifoWritePos -1 )] = 37 | 0x80;
+          memory[RAM_RXFIFO + ((rxfifoWritePos + 128 -1) & 127)] = 37 | 0x80;
           setFIFOP(true);
           setSFD(false);
           lastPacketStart = (rxfifoWritePos + 128 - rxlen) & 127;
@@ -596,7 +597,7 @@
         if(rxfifoLen == 0)
           break;
         if(DEBUG) log("RXFIFO READ " + rxfifoReadPos + " => " +
-            (memory[RAM_RXFIFO + rxfifoReadPos] & 0xFF) );
+            (memory[RAM_RXFIFO + rxfifoReadPos] & 0xFF) + " size: " + rxfifoLen);
         source.byteReceived( (memory[RAM_RXFIFO + rxfifoReadPos] & 0xFF) );
         rxfifoReadPos++;
 
@@ -615,7 +616,7 @@
         // -MT FIFOP is lowered when there are less than IOCFG0:FIFOP_THR bytes in the RXFIFO
         // If FIFO_THR is greater than the frame length, FIFOP goes low when the first byte is read out.
         // As long as we are in "OVERFLOW" the fifoP is not cleared.
-        if (fifoP && stateMachine != RadioState.RX_OVERFLOW) {
+        if (fifoP && !overflow) {
           if (DEBUG) log("*** FIFOP cleared at: " + rxfifoReadPos +
               " lastPacketStartPos: " + lastPacketStart);
           setFIFOP(false);
@@ -778,7 +779,12 @@
       if (DEBUG) log("Completed Transmission.");
       status &= ~STATUS_TX_ACTIVE;
       setSFD(false);
-      setState(RadioState.RX_CALIBRATE);
+      if (overflow) {
+        /* TODO: is it going back to overflow here ?=? */
+        setState(RadioState.RX_OVERFLOW);
+      } else {
+        setState(RadioState.RX_CALIBRATE);
+      }
       txfifoFlush = true;
     }
   }
@@ -812,6 +818,9 @@
     setSFD(false);
     setFIFOP(false);
     setFIFO(false);
+    overflow = false;
+    /* goto RX Calibrate */
+    setState(RadioState.RX_SFD_SEARCH);
   }
 
   // TODO: update any pins here?
@@ -879,6 +888,7 @@
     if (DEBUG) log("RXFIFO Overflow! Read Pos: " + rxfifoReadPos + " Write Pos: " + rxfifoWritePos);
     setFIFOP(true);
     setFIFO(false);
+    overflow = true;
     setState(RadioState.RX_OVERFLOW);
   }
   


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