From: <fro...@us...> - 2008-09-18 04:19:34
|
Revision: 337 http://mspsim.svn.sourceforge.net/mspsim/?rev=337&view=rev Author: fros4943 Date: 2008-09-18 11:19:32 +0000 (Thu, 18 Sep 2008) Log Message: ----------- debug output (false) Modified Paths: -------------- mspsim/se/sics/mspsim/chip/CC2420.java mspsim/se/sics/mspsim/chip/SHT11.java Modified: mspsim/se/sics/mspsim/chip/CC2420.java =================================================================== --- mspsim/se/sics/mspsim/chip/CC2420.java 2008-09-17 12:10:18 UTC (rev 336) +++ mspsim/se/sics/mspsim/chip/CC2420.java 2008-09-18 11:19:32 UTC (rev 337) @@ -254,7 +254,7 @@ if( (registers[REG_IOCFG1] & CCAMUX) == CCA_XOSC16M_STABLE) { setCCA(true); } else { - System.out.println("CC2420: CCAMUX != CCA_XOSC16M_STABLE! Not raising CCA"); + if(DEBUG) System.out.println("CC2420: CCAMUX != CCA_XOSC16M_STABLE! Not raising CCA"); } } }; @@ -400,7 +400,7 @@ rxfifo_len++; if(rxfifo_write_pos == 128) { - System.out.println("Wrapped RXFIFO write pos"); + if (DEBUG) System.out.println("Wrapped RXFIFO write pos"); rxfifo_write_pos = 0; } @@ -515,7 +515,7 @@ case READ_RXFIFO: if(rxfifo_len == 0) break; - System.out.println("CC2420: RXFIFO READ " + rxfifo_read_pos + " => " + + if(DEBUG) System.out.println("CC2420: RXFIFO READ " + rxfifo_read_pos + " => " + (memory[RAM_RXFIFO + rxfifo_read_pos] & 0xFF) ); source.byteReceived( (memory[RAM_RXFIFO + rxfifo_read_pos] & 0xFF) ); rxfifo_read_pos++; @@ -603,7 +603,7 @@ //} setMode(MODE_RX_ON); }else{ - System.out.println("CC2420: WARNING: SRXON when not IDLE"); + if (DEBUG) System.out.println("CC2420: WARNING: SRXON when not IDLE"); } break; @@ -641,7 +641,7 @@ setState(STATE_TX_CALIBRATE); setMode(MODE_TXRX_ON); }else{ - System.out.println("CC2420: STXONCCA Ignored, CCA false"); + if (DEBUG) System.out.println("CC2420: STXONCCA Ignored, CCA false"); } } break; @@ -781,7 +781,7 @@ if(on) { // 0.6ms maximum vreg startup from datasheet pg 13 cpu.scheduleTimeEventMillis(vregEvent, 0.1); - System.out.println(getName() + ": Scheduling vregEvent at: cyc = " + cpu.cycles + + if (DEBUG) System.out.println(getName() + ": Scheduling vregEvent at: cyc = " + cpu.cycles + " target: " + vregEvent.getTime() + " current: " + cpu.getTime()); }else{ this.on = on; Modified: mspsim/se/sics/mspsim/chip/SHT11.java =================================================================== --- mspsim/se/sics/mspsim/chip/SHT11.java 2008-09-17 12:10:18 UTC (rev 336) +++ mspsim/se/sics/mspsim/chip/SHT11.java 2008-09-18 11:19:32 UTC (rev 337) @@ -51,6 +51,8 @@ private static final int COMMAND = 1; private static final int ACK_CMD = 2; + private final boolean DEBUG = false; + private final static char[] INIT_COMMAND = "CdcCD".toCharArray(); private int initPos = 0; @@ -87,7 +89,7 @@ public void clockPin(boolean high) { if (clockHi == high) return; char c = high ? 'C' : 'c'; - System.out.println(getName() + ": clock pin " + c); + if (DEBUG) System.out.println(getName() + ": clock pin " + c); switch (state) { case IDLE: if (checkInit(c)) { @@ -117,7 +119,7 @@ public void dataPin(boolean high) { if (dataHi == high) return; char c = high ? 'D' : 'd'; - System.out.println(getName() + ": data pin " + c); + if (DEBUG) System.out.println(getName() + ": data pin " + c); switch (state) { case IDLE: if (checkInit(c)) { @@ -132,7 +134,9 @@ initPos++; if (initPos == INIT_COMMAND.length) { initPos = 0; - System.out.println("SHT11: COMMAND signature detected!!!"); + if (DEBUG) { + System.out.println("SHT11: COMMAND signature detected!!!"); + } return true; } } else { This was sent by the SourceForge.net collaborative development platform, the world's largest Open Source development site. |