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<title>datasheet for multi_processor</title>
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| multi_processor |
|
| 2013.01.08.18:52:07 | Datasheet |
Overview
| clk_0 | multi_processor |
| led | |
| out_port | |
Processors
cpu1 Nios II 12.0
cpu2 Nios II 12.0
All Components
cpu1 altera_nios2_qsys 12.0
cpu2 altera_nios2_qsys 12.0
timer1 altera_avalon_timer 12.0
timer2 altera_avalon_timer 12.0
mutex_0 altera_avalon_mutex 12.0
jtag_uart1 altera_avalon_jtag_uart 12.0
jtag_uart2 altera_avalon_jtag_uart 12.0
sysid altera_avalon_sysid_qsys 12.0
led altera_avalon_pio 12.0
sdram_0 altera_avalon_new_sdram_controller 12.0
cpu1 Nios II 12.0
cpu2 Nios II 12.0
All Components
cpu1 altera_nios2_qsys 12.0
cpu2 altera_nios2_qsys 12.0
timer1 altera_avalon_timer 12.0
timer2 altera_avalon_timer 12.0
mutex_0 altera_avalon_mutex 12.0
jtag_uart1 altera_avalon_jtag_uart 12.0
jtag_uart2 altera_avalon_jtag_uart 12.0
sysid altera_avalon_sysid_qsys 12.0
led altera_avalon_pio 12.0
sdram_0 altera_avalon_new_sdram_controller 12.0
Memory Map
| cpu1 | cpu2 | |||
| data_master | instruction_master | data_master | instruction_master | |
| cpu1 | ||||
| jtag_debug_module | 0x08000800 | 0x08000800 | ||
| cpu2 | ||||
| jtag_debug_module | 0x00000800 | 0x00000800 | ||
| timer1 | ||||
| s1 | 0x08001000 | |||
| timer2 | ||||
| s1 | 0x00001000 | |||
| mutex_0 | ||||
| s1 | 0x08001038 | 0x08001038 | ||
| jtag_uart1 | ||||
| avalon_jtag_slave | 0x08001030 | |||
| jtag_uart2 | ||||
| avalon_jtag_slave | 0x00001020 | |||
| sysid | ||||
| control_slave | 0x08001040 | |||
| led | ||||
| s1 | 0x08001020 | 0x08001020 | ||
| sdram_0 | ||||
| s1 | 0x04000000 | 0x04000000 | 0x04000000 | 0x04000000 |
clk_0
clock_source v12.0
Parameters
|
Software Assignments(none) |
cpu1
altera_nios2_qsys v12.0| clk_0 | clk | cpu1 | |
| clk | |||
| clk_reset | |||
| reset_n | |||
| data_master | timer1 | ||
| s1 | |||
| d_irq | |||
| irq | |||
| data_master | jtag_uart1 | ||
| avalon_jtag_slave | |||
| d_irq | |||
| irq | |||
| data_master | mutex_0 | ||
| s1 | |||
| data_master | sysid | ||
| control_slave | |||
| data_master | led | ||
| s1 | |||
| data_master | sdram_0 | ||
| s1 | |||
| instruction_master | |||
| s1 |
Parameters
|
Software Assignments
|
cpu2
altera_nios2_qsys v12.0| clk_0 | clk | cpu2 | |
| clk | |||
| clk_reset | |||
| reset_n | |||
| data_master | timer2 | ||
| s1 | |||
| d_irq | |||
| irq | |||
| data_master | mutex_0 | ||
| s1 | |||
| data_master | jtag_uart2 | ||
| avalon_jtag_slave | |||
| d_irq | |||
| irq | |||
| data_master | led | ||
| s1 | |||
| data_master | sdram_0 | ||
| s1 | |||
| instruction_master | |||
| s1 |
Parameters
|
Software Assignments
|
timer1
altera_avalon_timer v12.0
Parameters
|
Software Assignments
|
timer2
altera_avalon_timer v12.0
Parameters
|
Software Assignments
|
mutex_0
altera_avalon_mutex v12.0
Parameters
|
Software Assignments
|
jtag_uart1
altera_avalon_jtag_uart v12.0
Parameters
|
Software Assignments
|
jtag_uart2
altera_avalon_jtag_uart v12.0
Parameters
|
Software Assignments
|
sysid
altera_avalon_sysid_qsys v12.0
Parameters
|
Software Assignments
|
led
altera_avalon_pio v12.0
Parameters
|
Software Assignments
|
sdram_0
altera_avalon_new_sdram_controller v12.0| clk_0 | clk | sdram_0 |
| clk | ||
| clk_reset | ||
| reset | ||
| cpu1 | data_master | |
| s1 | ||
| instruction_master | ||
| s1 | ||
| cpu2 | data_master | |
| s1 | ||
| instruction_master | ||
| s1 |
Parameters
|
Software Assignments
|
| generation took 0.01 seconds | rendering took 0.11 seconds |
