Monsputer project / Blog: Recent posts

Same bug corrected on the other SPI port

The MISO missed one shift clock.

I'm currently canning all the boards I made up to date. This will be the version 1 of the Monsputer.

The RomWBW version of CP/M supports only 16 vectors in mode 2. I reassigned the interrupts in order to only use 16 vectors instead of 24. The unused interrupts can be polled instead.
On the CAN-I²C card, no hardware changes were needed. The only changes will be the interrupt levels in the CPLD.

I reached a significant milestone a few months ago. I succeeded porting CP/M 2.2 to the monsputer.
Seeing it running Turbo Pascal and Word Star was quite a blast!
Next step is to make it run a version of CP/M 3. Using RomWBW made by Wayne Warthen seems to be the easiest way.
Already, the monsputer has many of the supported peripherals.

While at it, I made a PCB from several designs for the RC2014 computers that are supported by RomWBW
PPIDE hard disk interface,
TMS9918A video interface,
VIA 82C42 keyboard interface,
WD37C65 floppy disk interface.

I made a Z80 interrupt controller for use in a CPLD. For those who would like to implement it with discrete logic, here's my old version of the controller.

See schematic interrupts-ports-bw.pdf or the Eagle version: interrupts-ports.sch

In this schematic, common 7474 chips can be used instead of the 74107 that I had at hand.
The interrupt enable register is R/W. Active level is low. It can be changed to high by replacing the 7432s with 7400 and using the Q outputs from the FFs instead of the /Q outputs.... read more

This debugging marathon finally brings the interrupt system into a stable, working condition.

An interrupt output was generated when enabling an interrupt while an interrupt input was active (not good).
I corrected the interrupt enabling circuit so that interrupts are generated only by transitions of the interrupt input lines.

The interrupt line was inducing glitchs on the reset line, causing it to reset the Interrupt Enable Register in the CPLD. Corrected this by adding a 1nF capacitor on the reset line of the CAN I²C board.... read more

After an intense debugging session, I got the interrupts working again.
It somehow worked previously but a few mishaps happened and some chips were busted. Also, a few miswirings were hidden deep in the circuits.

After a debugging marathon, here's a working version.

Corrected address decode for CAN chip (SJA1000) to allow PeliCAN mode.
Corrected the interrupt circuit to send INT signal

Minor fixups, small modif for an-timer board

Relocated some signals:
/RD moved on pin 84 which is a global output enable
A1 moved on pin 21
pin 44 is free

Corrected the address range for the 6821 chip

The hardware needed some rework in order to support CP/M. Instead of paging memory in 8000-FFFF, pages are now remapped to 0000-7FFF.
The bios needed some modification to use the common memory, now at 8000-FFFF.
The Z80 CPU board's CPLD needed some modification also to be able to copy the ROM into RAM at same address and switch from ROM to RAM.
Also, the memory expension boards had to remap 32k pages to 0000-7FFF.
Bios-7.0 was the last version before the modif. Bios-8.0 is the version that supports CP/M.

I will try to modify my system to run CP/M with support for either SD card, compact flash or a Vinculum USB flash reader.
This will affect the hardware and software, and many CPLD will have to be modified.

I upgraded the SPI ports for these boards: Analog + timers and Serial board (CAN, I²C, SPI, Parallel).

After a brief test of the SPI port, a rework was necessary to get it to work perfectly. I used Logisim Evolution to design the circuit to be implemented in a CPLD.

In the monsputer-xxxxxx.tar.bz2 file,
In the soft/firmware/eprom_bank folder, I implemented some maths in floating point using 8 bytes per float.
The routines implement the 4 basic maths operations.

These routines came from the TAB book N. 952
"Microprocessor programming for computer hobbyists" By Neill Graham 1977
ISBN 0-8306-6952-3

They were written in an extension of PL/M, a PL/I-like language developped for the Intel 8080.
I hand compiled this for SDCC, with the use of the Z80 Preprocessor and the Structured Z80 processor.... read more

This summer, I finished the last board. I began doing some tests, all worked, but some (electrical) accidents happened and the system was beginning to be unstable.
Debugging took too much time, and all other projects crawled to a stop. Priorities were setted, and the Monsputer barely escaped being trashed.
The Monsputer project will sleep for a while.

The Z80 CPU clean up is done and debugged. I also made a Monsputer probe and a bus display: this board reads the entire bus and sends it to a PC. It can single-step the CPU.

I'm currently modifying the CPU board to make a cleaner version. A bigger (physically smaller!) CPLD will make the design more clean.

I've done some firmware to interface with the VDIP2 module from FTDI.
The glue logic makes the module directly accessible to the Z80 through a data and a command/status port. 2 register bits in the control register are provided to enable the receive and transmit interrupts.
Both transmit and receive use interrupts.
Routines may be included in the next bios (v5).