Brian G VanBuren
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2007-03-21
- priority: 6 --> 8
Provide latch register (aka if clocked this cycle, assign a value, should treat as clocked component.
Also, provide SR latch, not(SR) latch, D latch, SR flip flop, T flip flop, JK flip flop, and D flip flops. These are helpful since they cannot be implemented at a lower level due to the one level pass simulation per clock.