Hi, Guys:
     I tried to port Mesa3D, DRI/DRM, x86 DDX driver into RTOS embedded env. So far
everything is running through after I fixed a lot of porting issues.
    Now I can get minglx demo running into ATI r300 command engine, gart table
setup looks OK. but the wierd problem is that I didn't get anything on screen.
    Does anybody know if I miss anyting here and need any special setting on ATI R300 chip?
FYI, I attach my log here.

    Thanks in advance!

    David


-----------------------------------------------------------------------------------------------
got MMIOAddress 0xfd9f0000
shared virtual width is 1024
 
PCI card detected
drm_ctxbitmap_next bit : 0
drm_ctxbitmap_init : 0
Initialized drm driver
offset = 0x00000000, size = 0x00002000, type = 2
8192 13 0x4cf8000
Added map 2 0x4cf8000/0x2000
offset = 0xfd9f0000, size = 0x00010000, type = 1
Added map 1 0xfd9f0000/0x10000
offset = 0xfa000000, size = 0x02000000, type = 0
Added map 0 0xfa000000/0x2000000
 
open_count = 0
 
offset = 0x00000000, size = 0x00002000, type = 2
Found kernel map 2
Added map 2 0x4cf8000/0x2000
[drm] added 8192 byte SAREA at 0x04cf8000
[drm] mapped SAREA 0x04cf8000 to 0x4cf8000, size 8192
offset = 0xfa000000, size = 0x02000000, type = 0
Found kernel map 0
Added map 0 0xfa000000/0x2000000
[drm] framebuffer handle = 0xfa000000
offset = 0xfd9f0000, size = 0x00010000, type = 1
Found kernel map 1
Added map 1 0xfd9f0000/0x10000
[drm] register handle = 0xfd9f0000
drm_sg_alloc
sg size=8388608 pages=2048
sg alloc handle  = 050ad000
[pci] 8192 kB allocated with handle 0x050ad000
offset = 0x00000000, size = 0x00101000, type = 4
Added map 4 0x50ad000/0x101000
[pci] ring handle = 0x050ad000
offset = 0x00101000, size = 0x00001000, type = 4
Added map 4 0x51ae000/0x1000
[pci] ring read ptr handle = 0x051ae000
offset = 0x00102000, size = 0x00200000, type = 4
Added map 4 0x51af000/0x200000
[pci] vertex/indirect buffers handle = 0x051af000
offset = 0x00302000, size = 0x004e0000, type = 4
Added map 4 0x53af000/0x4e0000
[pci] GART texture map handle = 0x053af000
Using 8 MB AGP aperture
Using 1 MB for the ring buffer
Using 2 MB for vertex/indirect buffers
Using 1 MB for AGP textures
Will use back buffer at offset 0x300000
Will use depth buffer at offset 0x600000
Will use 23552 kb for textures at offset 0x900000
drm_ctxbitmap_next bit : 1
1
1 (pid 84450672) requests lock (0x00000000), flags = 0x00000000
1 has lock
 
dev_priv->cp_ring->handle 0x50ad000
dev_priv->ring_rptr->handle 0x51ae000
dev->agp_buffer_map->handle 0x51af000
  mem_size         : 0x04000000
  MC_FB_LOCATION   : 0xfbfff800
  FB_LOCATION  : 0xfa000000
dev_priv->gart_size 8388608
dev_priv->gart_vm_start 0xfc000000
dev_priv->gart_buffers_offset 0xfc102000
Setting phys_pci_gart to 0xfbff8000 01FF8000
programming pcie FC000000 FBFF8000 00800000
RADEON_PCIE_TX_DISCARD_RD_ADDR_LO = 0x00000000
RADEON_PCIE_TX_GART_BASE = 0x00000000
RADEON_PCIE_TX_GART_START_LO = 0x00000000
RADEON_PCIE_TX_GART_END_LO = 0x00000000
RADEON_PCIE_TX_DISCARD_RD_ADDR_LO = 0xfc000000
RADEON_PCIE_TX_GART_BASE = 0xfbff8000
RADEON_PCIE_TX_GART_START_LO = 0xfc000000
RADEON_PCIE_TX_GART_END_LO = 0xfc7ff000
 
Loading R300 Microcode
RADEON_MC_FB_LOCATION = 0x00ff0000
ring rptr: offset=0x051ae000 handle=0x051ae000
writeback test succeeded, tmp=1
 
 
RADEONEngineRestore
 
 
RADEON_CP_CSQ_AVAIL = 0x100400fa
RADEON_CP_CNTL = 0x40000000
RADEON_CP_CSQ_DATA = 0xffffffff
RADEON_CP_CSQ_MODE = 0x00004d4d
RADEON_CP_CSQ_STAT = 0x10001806
RADEON_CP_ME_CNTL = 0x4000ffff
RADEON_CP_ME_RAM_ADDR = 0x00000000
RADEON_CP_RB_CNTL = 0x00000011
RADEON_CP_STAT = 0x80000004
RBBM_STATUS = 0x00000140
RADEON_RB_BASE = 0xfc000000
CP_RB_RTPR = 0x00000006
CP_RB_WTPR = 0x00000006
count:      32
order:      16
size:       65536
agp_offset: 1056768
alignment:  65536
page_order: 4
total:      65536
buffer 0 @ 0x51af000
buffer 1 @ 0x51bf000
buffer 2 @ 0x51cf000
buffer 3 @ 0x51df000
buffer 4 @ 0x51ef000
buffer 5 @ 0x51ff000
buffer 6 @ 0x520f000
buffer 7 @ 0x521f000
buffer 8 @ 0x522f000
buffer 9 @ 0x523f000
buffer 10 @ 0x524f000
buffer 11 @ 0x525f000
buffer 12 @ 0x526f000
buffer 13 @ 0x527f000
buffer 14 @ 0x528f000
buffer 15 @ 0x529f000
buffer 16 @ 0x52af000
buffer 17 @ 0x52bf000
buffer 18 @ 0x52cf000
buffer 19 @ 0x52df000
buffer 20 @ 0x52ef000
buffer 21 @ 0x52ff000
buffer 22 @ 0x530f000
buffer 23 @ 0x531f000
buffer 24 @ 0x532f000
buffer 25 @ 0x533f000
buffer 26 @ 0x534f000
buffer 27 @ 0x535f000
buffer 28 @ 0x536f000
buffer 29 @ 0x537f000
buffer 30 @ 0x538f000
buffer 31 @ 0x539f000
byte_count: 2097152
dma->buf_count : 32
entry->buf_count : 32
[drm] Added 32 65536 byte vertex/indirect buffers
1:0:0 => IRQ 9
drm_irq_install: irq=9
[drm] dma control initialized, using IRQ 9
[drm] Initialized kernel gart heap manager, 5111808
color tiling disabled
page flipping disabled
open_count = 0
32 buffers, retcode = 84585816
    returning 84585816
32 buffers, retcode = 0
1
drawable is 1 0x2ebc12bc
drm_ctxbitmap_next bit : 2
2
Mesa: CPU vendor: GenuineIntel
Mesa: CPU name: Intel(R) Core(TM) Duo CPU      L2400  @ 1.66GHz
Mesa: Mesa 6.5.3 DEBUG build May 18 2009 06:02:37
Mesa: MESA_NO_DITHER set - dithering disabled
Updated 1 cliprects for drawable 0
Mesa: Mesa GL_VERSION = 1.3 Mesa 6.5.3
Mesa: Mesa GL_RENDERER = Mesa DRI R300 20060815 TCL
Mesa: Mesa GL_VENDOR = DRI R300 Project
Mesa: Mesa GL_EXTENSIONS = GL_ARB_fragment_program GL_ARB_imaging GL_ARB_multisample
GL_ARB_multitexture GL_ARB_texture_border_clamp GL_ARB_texture_compression GL_ARB_tex
ture_cube_map GL_ARB_texture_env_add GL_ARB_texture_env_combine GL_ARB_texture_env_cr
ossbar GL_ARB_texture_env_dot3 GL_MESAX_texture_float GL_ARB_texture_mirrored_repeat
GL_ARB_texture_rectangle GL_ARB_transpose_matrix GL_ARB_vertex_buffer_object GL_ARB_v
ertex_program GL_ARB_window_pos GL_EXT_abgr GL_EXT_bgra GL_EXT_blend_color GL_EXT_ble
nd_equation_separate GL_EXT_blend_func_separate GL_EXT_blend_minmax GL_EXT_blend_subt
ract GL_EXT_clip_volume_hint GL_EXT_compiled_vertex_array GL_EXT_convolution GL_EXT_c
opy_texture GL_EXT_draw_range_elements GL_EXT_gpu_program_parameters GL_EXT_histogram
 GL_EXT_packed_pixels GL_EXT_polygon_offset GL_EXT_rescale_normal GL_EXT_secondary_co
lor GL_EXT_separate_specular_color GL_EXT_stencil_two_side GL_EXT_stencil_wrap GL_EXT
_subtexture GL_EXT_texture GL_EXT_texture3D GL_EXT_texture_edge_clamp GL_EXT_texture_
env_add GL_EXT_texture_env_combine GL_EXT_texture_env_dot3 GL_EXT_texture_filter_anis
otropic GL_EXT_texture_lod_bias GL_EXT_texture_mirror_clamp GL_EXT_texture_object GL_
EXT_texture_rectangle GL_EXT_vertex_array GL_APPLE_packed_pixels GL_ATI_blend_equatio
n_separate GL_ATI_texture_env_combine3 GL_ATI_texture_mirror_once GL_IBM_rasterpos_cl
ip GL_IBM_texture_mirrored_repeat GL_INGR_blend_func_separate GL_MESA_pack_invert GL_
MESA_ycbcr_texture GL_MESA_window_pos GL_NV_blend_square GL_NV_light_max_exponent GL_
NV_texture_rectangle GL_NV_texgen_reflection GL_NV_vertex_program GL_OES_read_format
GL_SGI_color_matrix GL_SGI_color_table GL_SGIS_generate_mipmap GL_SGIS_texture_border
_clamp GL_SGIS_texture_edge_clamp GL_SGIS_texture_lod
Mesa: Mesa thread-safe: YES
Mesa: Mesa x86-optimized: YES
Mesa: Mesa sparc-optimized: NO
2 (pid 84450672) requests lock (0x00000000), flags = 0x00000000
2 has lock
*********************************WARN_ONCE*********************************
r300_translate_vertex_shader line 446
Ran out of temps, num temps 31, us 13
***************************************************************************
allocated 1 at age 0
offset=00000000
offset=00000020
radeon_mm_use: 1 at age 0
radeon_mm_use: 1 at age 0
 
1 cliprects
R300_CMD_WAIT
R300_CMD_PACKET0
R300_CMD_END3D
R300_CMD_WAIT
R300_CMD_PACKET0
R300_CMD_END3D
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_VPU
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_VPU
R300_CMD_WAIT
R300_CMD_END3D
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET3
R300_CMD_PACKET3_CLEAR
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_WAIT
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_WAIT
R300_CMD_PACKET0
R300_CMD_END3D
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_VPU
R300_CMD_VPU
R300_CMD_PACKET3
R300_CMD_PACKET3_RAW
R300_CMD_PACKET3
R300_CMD_PACKET3_RAW
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_SCRATCH
R300_CMD_SCRATCH
radeon_status:
RBBM_STATUS = 0x00000140
CP_RB_RTPR = 0x00000006
CP_RB_WTPR = 0x00000006
RADEON_CP_CSQ_AVAIL = 0x10040100
RADEON_CP_CNTL = 0x40000000
RADEON_CP_CSQ_DATA = 0xffffffff
RADEON_CP_CSQ_MODE = 0x00004d4d
RADEON_CP_CSQ_STAT = 0x10001806
RADEON_CP_ME_CNTL = 0x4000ffff
RADEON_CP_ME_RAM_ADDR = 0x00000000
RADEON_CP_RB_CNTL = 0x00000011
RADEON_CP_STAT = 0x80000004
END
 
 
dispatch swap 0,0-300,300
offset=00000060
offset=00000080
radeon_mm_use: 1 at age 2
radeon_mm_use: 1 at age 2
 
1 cliprects
R300_CMD_WAIT
R300_CMD_PACKET0
R300_CMD_END3D
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_VPU
R300_CMD_VPU
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_VPU
R300_CMD_WAIT
R300_CMD_END3D
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET3
R300_CMD_PACKET3_CLEAR
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_WAIT
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_WAIT
R300_CMD_PACKET0
R300_CMD_END3D
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_VPU
R300_CMD_VPU
R300_CMD_PACKET3
R300_CMD_PACKET3_RAW
R300_CMD_PACKET3
R300_CMD_PACKET3_RAW
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_SCRATCH
R300_CMD_SCRATCH
radeon_status:
RBBM_STATUS = 0x00000140
CP_RB_RTPR = 0x00000217
CP_RB_WTPR = 0x00000217
RADEON_CP_CSQ_AVAIL = 0x10040100
RADEON_CP_CNTL = 0x40000000
RADEON_CP_CSQ_DATA = 0xffffffff
RADEON_CP_CSQ_MODE = 0x00004d4d
RADEON_CP_CSQ_STAT = 0x10005c17
RADEON_CP_ME_CNTL = 0x4000ffff
RADEON_CP_ME_RAM_ADDR = 0x00000000
RADEON_CP_RB_CNTL = 0x00000011
RADEON_CP_STAT = 0x80000004
END
 
 
dispatch swap 0,0-300,300
offset=000000c0
offset=000000e0
radeon_mm_use: 1 at age 4
radeon_mm_use: 1 at age 4
 
1 cliprects
R300_CMD_WAIT
R300_CMD_PACKET0
R300_CMD_END3D
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_VPU
R300_CMD_VPU
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_VPU
R300_CMD_WAIT
R300_CMD_END3D
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET3
R300_CMD_PACKET3_CLEAR
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_WAIT
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_WAIT
R300_CMD_PACKET0
R300_CMD_END3D
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_VPU
R300_CMD_VPU
R300_CMD_PACKET3
R300_CMD_PACKET3_RAW
R300_CMD_PACKET3
R300_CMD_PACKET3_RAW
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_SCRATCH
R300_CMD_SCRATCH
radeon_status:
RBBM_STATUS = 0x00000140
CP_RB_RTPR = 0x00000443
CP_RB_WTPR = 0x00000443
RADEON_CP_CSQ_AVAIL = 0x10040100
RADEON_CP_CNTL = 0x40000000
RADEON_CP_CSQ_DATA = 0xffffffff
RADEON_CP_CSQ_MODE = 0x00004d4d
RADEON_CP_CSQ_STAT = 0x10010c43
RADEON_CP_ME_CNTL = 0x4000ffff
RADEON_CP_ME_RAM_ADDR = 0x00000000
RADEON_CP_RB_CNTL = 0x00000011
RADEON_CP_STAT = 0x80000004
END
 
 
dispatch swap 0,0-300,300
offset=00000120
offset=00000140
radeon_mm_use: 1 at age 6
radeon_mm_use: 1 at age 6
 
1 cliprects
R300_CMD_WAIT
R300_CMD_PACKET0
R300_CMD_END3D
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_VPU
R300_CMD_VPU
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_VPU
R300_CMD_WAIT
R300_CMD_END3D
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET3
R300_CMD_PACKET3_CLEAR
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_WAIT
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_WAIT
R300_CMD_PACKET0
R300_CMD_END3D
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_VPU
R300_CMD_VPU
R300_CMD_PACKET3
R300_CMD_PACKET3_RAW
R300_CMD_PACKET3
R300_CMD_PACKET3_RAW
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_SCRATCH
R300_CMD_SCRATCH
radeon_status:
RBBM_STATUS = 0x00000140
CP_RB_RTPR = 0x0000066f
CP_RB_WTPR = 0x0000066f
RADEON_CP_CSQ_AVAIL = 0x10040100
RADEON_CP_CNTL = 0x40000000
RADEON_CP_CSQ_DATA = 0xffffffff
RADEON_CP_CSQ_MODE = 0x00004d4d
RADEON_CP_CSQ_STAT = 0x1001bc6f
RADEON_CP_ME_CNTL = 0x4000ffff
RADEON_CP_ME_RAM_ADDR = 0x00000000
RADEON_CP_RB_CNTL = 0x00000011
RADEON_CP_STAT = 0x80000004
END
 
 
dispatch swap 0,0-300,300
offset=00000180
offset=000001a0
radeon_mm_use: 1 at age 8
radeon_mm_use: 1 at age 8
 
1 cliprects
R300_CMD_WAIT
R300_CMD_PACKET0
R300_CMD_END3D
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_VPU
R300_CMD_VPU
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_VPU
R300_CMD_WAIT
R300_CMD_END3D
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET3
R300_CMD_PACKET3_CLEAR
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_WAIT
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_WAIT
R300_CMD_PACKET0
R300_CMD_END3D
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_VPU
R300_CMD_VPU
R300_CMD_PACKET3
R300_CMD_PACKET3_RAW
R300_CMD_PACKET3
R300_CMD_PACKET3_RAW
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_SCRATCH
R300_CMD_SCRATCH
radeon_status:
RBBM_STATUS = 0x00000140
CP_RB_RTPR = 0x0000089b
CP_RB_WTPR = 0x0000089b
RADEON_CP_CSQ_AVAIL = 0x10040100
RADEON_CP_CNTL = 0x40000000
RADEON_CP_CSQ_DATA = 0xffffffff
RADEON_CP_CSQ_MODE = 0x00004d4d
RADEON_CP_CSQ_STAT = 0x10026c9b
RADEON_CP_ME_CNTL = 0x4000ffff
RADEON_CP_ME_RAM_ADDR = 0x00000000
RADEON_CP_RB_CNTL = 0x00000011
RADEON_CP_STAT = 0x80000004
END
 
 
dispatch swap 0,0-300,300
offset=000001e0
offset=00000200
radeon_mm_use: 1 at age a
radeon_mm_use: 1 at age a
 
1 cliprects
R300_CMD_WAIT
R300_CMD_PACKET0
R300_CMD_END3D
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_VPU
R300_CMD_VPU
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_VPU
R300_CMD_WAIT
R300_CMD_END3D
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET3
R300_CMD_PACKET3_CLEAR
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_WAIT
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_WAIT
R300_CMD_PACKET0
R300_CMD_END3D
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_VPU
R300_CMD_VPU
R300_CMD_PACKET3
R300_CMD_PACKET3_RAW
R300_CMD_PACKET3
R300_CMD_PACKET3_RAW
R300_CMD_PACKET0
R300_CMD_PACKET0
R300_CMD_SCRATCH
R300_CMD_SCRATCH
radeon_status:
RBBM_STATUS = 0x00000140
CP_RB_RTPR = 0x00000ac7
CP_RB_WTPR = 0x00000ac7
RADEON_CP_CSQ_AVAIL = 0x10040100
RADEON_CP_CNTL = 0x40000000
RADEON_CP_CSQ_DATA = 0xffffffff
RADEON_CP_CSQ_MODE = 0x00004d4d
RADEON_CP_CSQ_STAT = 0x10031cc7
RADEON_CP_ME_CNTL = 0x4000ffff
RADEON_CP_ME_RAM_ADDR = 0x00000000
RADEON_CP_RB_CNTL = 0x00000011
RADEON_CP_STAT = 0x80000004
END
 
 
dispatch swap 0,0-300,300

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