Mark3 RTOS Source

-SAM D20 Port now supports tickless timers via the TC module, clocked off of GCLK_0.
-Tested using the kernel sanity test suite from Atmel Studio 6.1

Updates to SAMD20 port, including a simple write-only serial driver, and better critical-section logic.

Fixed 328p tickless timer implementation that was broken after adding optional tick-based timer.

Adding samd20 port, based on the working code debugged on-device through the Xplained board

Submitting *working* Cortex-M0 code against the stm32f0 target, even though it's been tested against SAM D20

Note: At this point, I have verified correct threading and functional timers on real CM0. M0 should now be considered "Alpha" quality

Fixed timer config for mega328p tick-based timers.

Adding preliminary tick-based timer support. Still failing sanity tests right now, need to sort that out...

-After a couple of days reading the ARM docs for CM0, and messing with GCC's inline assembly syntax (it's *so* intuitive... ), I think I've got a workable context switch/thread-start.
-My stm32f0 board has the world's worst onboard debugger, so I need to order something better to test with.
-Also, let it be known that the code density on Cortex M0 is really not that great. The kernel compiles to about 48K with -0s...

-Initial checkin of platform support for ARM Cortex-M0 parts, targetting stm32f0/GCC (since that's the board I have). Toolchain is working - code gets generated, libraries get built.
-Kernel port for CM0, however, is just a stub at this point, need to implement NVIC code for SysTick timer, as well as the gross inline-assembly for context switching.
-There's no board-specific init code tied into Mark3, so that would need to be linked in as well for any example code. Really, example code will have to be abstracted out by platform going forward
-Fixed some default usage of K_UCHAR arrays as the stack - Implemented new K_WORD type for platform-specific register word-width.

Adding DCPU assembler file for "hello world" to the DCPU examples folder