[sara <schane@os...>]

Hi Brett,

Have you found any solution to this fatal interrupt ? what could be the source of this issue ?

Sara

>> -----Original Message-----
>> From: Pavel Roskin [mailto:proski@...]
>> Sent: Friday, 17 July 2009 12:17 PM
>> To: Brett Wright
>> Cc: sara; madwifi-users@...
>> Subject: Re: [Madwifi-users] fatal interrupt
>>
>> Where did you get it?  Google cannot find the above text.
>>
>> Maybe you could verify the value?  There is a discrepancy between the
>> FreeBSD HAL used in MadWifi and ar5k used in OpenBSD.
>>
>> This patch makes MadWifi use the values from ar5k.  Please test.
>>
>> Index: ath_hal/ar5212/ar5212reg.h
>> ===================================================================
>> --- ath_hal/ar5212/ar5212reg.h	(revision 4079)
>> +++ ath_hal/ar5212/ar5212reg.h	(working copy)
>> @@ -454,9 +454,9 @@
>>  #define AR_ISR_S1_QCU_TXEOL_S	16
>>
>>  #define	AR_ISR_S2_QCU_TXURN	0x000003FF /* Mask for TXURN
>>     
> (QCU 0-9)
>   
>> */
>> -#define	AR_ISR_S2_MCABT		0x00010000 /* Master cycle abort
>> interrupt */
>> -#define	AR_ISR_S2_SSERR		0x00020000 /* SERR interrupt */
>> -#define	AR_ISR_S2_DPERR		0x00040000 /* PCI bus parity
>>     
> error */
>   
>> +#define	AR_ISR_S2_MCABT		0x00100000 /* Master cycle abort
>> interrupt */
>> +#define	AR_ISR_S2_SSERR		0x00200000 /* SERR interrupt */
>> +#define	AR_ISR_S2_DPERR		0x00400000 /* PCI bus parity
>>     
> error */
>   
>>  #define	AR_ISR_S2_TIM		0x01000000 /* TIM */
>>  #define	AR_ISR_S2_CABEND	0x02000000 /* CABEND */
>>  #define	AR_ISR_S2_DTIMSYNC	0x04000000 /* DTIMSYNC */
>>
>> --
>> Regards,
>> Pavel Roskin
>>
>>
>>
>>     
>
> Hi Pavel,
>
> >From Atheros. It is specific for AR5213.
> I believe the #defines in Madwifi are correct - i.e. the MCABT bit is
> bit 16 of secondary interrupt status register 2. The values used by
> FreeBSD are incorrect based on the info I have.
>
> I can confirm that this is the bit I am seeing set:
> ar5212GetPendingInterrupts: fatal error, ISR_RAC=0x80000 ISR_S2_S
> =0x10000
>
> Brett
>   
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