Re: [LTP] [PATCH] Make crash01 invalidate icache on powerpc

[Mike F. <va...@ge...>]

On Thursday 15 June 2006 01:08, Olof Johansson wrote:
> On Thu, Jun 15, 2006 at 12:36:55AM -0400, Mike Frysinger wrote:
> > On Monday 12 June 2006 18:46, Olof Johansson wrote:
> > > POWER5 has coherent icache, but POWER4, PPC970 and some other
> > > processors lack it. The standard dcbst/icbi/isync is needed to avoid
> > > using the not so random (or stale) data instead.
> > >
> > > There doesn't seem to be a generic way to do this through libc, so add
> > > the assembly under ifdef.
> > >
> > > It'll do more flushes than needed (i.e. only one per line is needed,
> > > but it does one per byte), but it's not like this is highly performan=
ce
> > > critical path.
> >
> > huh ?  how is this specific to this ltp test ?  these sort of
> > cpu-workarounds belong in gcc or the kernel, not generic C code
>
> crash01 is a not normal software: It generates random data and tries to
> execute it as instructions. GCC has no way of knowing that this is to be
> done to it. Same thing with the kernel.

if the memory has executable permissions, execution of the memory is perfec=
tly=20
valid, regardless of what random crap is thrown into it

at the very least you could generalize it into a function=20
(ltp_invalid_icache()) and put it into the libltp.a
=2Dmike