From: Stuart M. <stu...@st...> - 2003-05-20 13:41:07
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Alex Abe-san found a similar problem when using my TLB miss handling patches. When using PIO there is no cache synchronisation in the generic IDE code, while NFS has an explicit call to flush_dcache_page. The solution we tried which has worked so far is based on the Sparc code, which redefines the IO functions to include a cache synchronisation call. The patch is attached. Abe-san has seen some problems when using DMA, which I've not been able to reproduce here, but PIO appears fine now. Stuart On Tue, 20 May 2003 11:07:42 +0100 ker...@be... wrote: > Hi, > > The reason we where seeing issues with executing from hard disk was due > to cache behaviour. We fixed it by applying this patch: > > --- ../../../linuxsh-2.4/include/asm-sh/pgtable.h 2003-04-10 > 17:19:24.000000000 +0100 > +++ pgtable.h 2003-05-20 10:56:26.000000000 +0100 > @@ -62,7 +62,7 @@ > extern void flush_icache_range(unsigned long start, unsigned long end); > extern void flush_cache_sigtramp(unsigned long addr); > > -#define flush_page_to_ram(page) do { } while (0) > +#define flush_page_to_ram(page) > flush_dcache_page(page) > #define flush_icache_page(vma,pg) do { } while (0) > > /* Initialization of P3 area for copy_user_page */ > > To ensure the data loaded from disk (with PIO) was properly cached in > the processor. We think this issue was avoided with booting from NFS > because of different cache behaviour when DMA is involved. > > flush_page_to_ram is a deprecated function but thats something that > would need to be sorted out in the main tree. Comments? > > -- > Alex, homepage: http://www.bennee.com/~alex/ > > There are only two kinds of men -- the dead and the deadly. > -- Helen Rowland > |