Re: [linuxsh-dev] SH7751R

[Matan Ziv-Av <ma...@sv...>]

On Wed, 19 Jun 2002, No Such User wrote:

> The SH7751R incorporates a 16-kbyte instruction cache (IC) for
> instructions and a 32-kbyte operand cache (OC) for data. Half of the
> operand cache memory (16 kbytes) can also be used as on-chip RAM. When
> the EMODE bit in the CCR register is cleared to 0 in the SH7751R, both
> the IC and OC are set to SH7751 compatible mode. Operation is as shown
> in table 4.1. When the EMODE bit in the CCR register is set to 1, the
> cache characteristics are as shown in table 4.2. After a power-on reset
> or manual reset, the initial value of the EMODE bit is 0.
> 
> I would have thought that all that needs to be done is to flip this bit
> during register initialisation of the processor.

For controlling the caches you need to implement functions to purge or
flush parts of the caches, and those are different when the cache is
larger and is associative (in the file arch/sh/mm/cache-sh4.c, and the
.S files in that directory).

> Matan - (sorry I'm new to the list) out of interest what board have you been
> using the 7751R on?

A custom board designed by the company that hires me - it includes SH4,
Ram, Rom and 3 ethernet controllers.

-- 
Matan Ziv-Av.                         ma...@sv...