Re: [linuxsh-dev] SH7751R

[No S. U. <no_...@ya...>]

----- Original Message -----
From: "Matan Ziv-Av" <ma...@sv...>
To: "NIIBE Yutaka" <gn...@m1...>
Cc: <lin...@li...>
Sent: Tuesday, June 18, 2002 9:58 AM
Subject: Re: [linuxsh-dev] SH7751R


> > Anyone try to port LinuxSH to that processor?
> >
> > I'm going to get the information...
As far as I understand the 'R' version is identical to the vanilla 7751 bar
the exception that it has an extended cache.

> The kernel (2.4.18 from the CVS) works, after a small fix in
> pci-sh7751.c to recognize the new PCI id. (This fix is in the patch I
> sent to this list for flexbox support).
>
> Using the extended cache (double size, 2-way associative) still eludes
> me. I hope someone else manages to do it.
Looking at the 7751 Hardware manual ADE-602-201B Rev 3.0 (4/11/2002) which
covers the 7751R, on page 87 :

The SH7751R incorporates a 16-kbyte instruction cache (IC) for
instructions and a 32-kbyte operand cache (OC) for data. Half of the
operand cache memory (16 kbytes) can also be used as on-chip RAM. When
the EMODE bit in the CCR register is cleared to 0 in the SH7751R, both
the IC and OC are set to SH7751 compatible mode. Operation is as shown
in table 4.1. When the EMODE bit in the CCR register is set to 1, the
cache characteristics are as shown in table 4.2. After a power-on reset
or manual reset, the initial value of the EMODE bit is 0.

I would have thought that all that needs to be done is to flip this bit
during register initialisation of the processor.

Matan - (sorry I'm new to the list) out of interest what board have you been
using the 7751R on?

Best Wishes,

~Pev


_________________________________________________________
Do You Yahoo!?
Get your free @yahoo.com address at http://mail.yahoo.com