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[linuxsh-dev] [PATCH] Wakeup UBC on startup
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From: Paul M. <pau...@ti...> - 2002-05-23 16:23:54
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Any objections to the following? I have a pesky SE7750 here that's been
putting the UBC to sleep on me, this patch fixes these issues. No idea
how many more of these are out there.
(Hopefully Evolution won't mangle this too badly.)
Regards,
--=20
Paul Mundt
pau...@ti...
TimeSys Corporation
2002-05-23 Paul Mundt <le...@ch...>
* arch/sh/Config.help, arch/sh/config.in, arch/sh/kernel/Makefile:
Add CONFIG_UBC_WAKEUP definitions.
* arch/sh/kernel/setup.c (setup_arch): Call ubc_wakeup() if
CONFIG_UBC_WAKEUP=3Dy.
* arch/sh/kernel/ubc.S: New file.
* include/asm-sh/ptrace.h: Move UBC definitions out to a UBC-specific
header.
* include/asm-sh/ubc.h: New file.
diff -x CVS -urN linux-sh-head.orig/arch/sh/Config.help linux-sh-head/arch/=
sh/Config.help
--- linux-sh-head.orig/arch/sh/Config.help Fri Mar 22 05:52:09 2002
+++ linux-sh-head/arch/sh/Config.help Thu May 23 12:10:07 2002
@@ -640,6 +640,14 @@
=20
If unsure, say N.
=20
+CONFIG_UBC_WAKEUP
+ Selecting this option will wakeup the User Break Controller (UBC) on
+ startup. Although the UBC is left in an awake state when the processor
+ comes up, some boot loaders misbehave by putting the UBC to sleep in a
+ power saving state, which causes issues with things like ptrace().
+
+ If unsure, say N.
+
CONFIG_SH_DMA
Selecting this option will provide same API as PC's Direct Memory
Access Controller(8237A) for SuperH DMAC.
diff -x CVS -urN linux-sh-head.orig/arch/sh/config.in linux-sh-head/arch/sh=
/config.in
--- linux-sh-head.orig/arch/sh/config.in Thu May 23 12:11:08 2002
+++ linux-sh-head/arch/sh/config.in Thu May 23 11:34:13 2002
@@ -161,6 +161,7 @@
int 'HD64465 IRQ' CONFIG_HD64465_IRQ 5
fi
=20
+bool 'Wakeup UBC on startup' CONFIG_UBC_WAKEUP
bool 'DMA controller (DMAC) support' CONFIG_SH_DMA
=20
bool 'PCI support' CONFIG_PCI
diff -x CVS -urN linux-sh-head.orig/arch/sh/kernel/Makefile linux-sh-head/a=
rch/sh/kernel/Makefile
--- linux-sh-head.orig/arch/sh/kernel/Makefile Mon Oct 15 16:44:47 2001
+++ linux-sh-head/arch/sh/kernel/Makefile Fri May 17 16:15:46 2002
@@ -16,7 +16,7 @@
=20
obj-y :=3D process.o signal.o entry.o traps.o irq.o irq_ipr.o \
ptrace.o setup.o time.o sys_sh.o semaphore.o \
- irq_imask.o io.o io_generic.o sh_ksyms.o
+ irq_imask.o io.o io_generic.o sh_ksyms.o ubc.o
=20
obj-$(CONFIG_CF_ENABLER) +=3D cf-enabler.o
obj-$(CONFIG_CPU_SH4) +=3D fpu.o
diff -x CVS -urN linux-sh-head.orig/arch/sh/kernel/setup.c linux-sh-head/ar=
ch/sh/kernel/setup.c
--- linux-sh-head.orig/arch/sh/kernel/setup.c Fri Mar 22 07:57:10 2002
+++ linux-sh-head/arch/sh/kernel/setup.c Thu May 23 12:09:23 2002
@@ -478,6 +478,17 @@
clear_thread_flag(TIF_USEDFPU);
current->used_math =3D 0;
#endif
+
+#ifdef CONFIG_UBC_WAKEUP
+ /*
+ * Some brain-damaged loaders decided it would be a good idea to put
+ * the UBC to sleep. This causes some issues when it comes to things
+ * like PTRACE_SINGLESTEP or doing hardware watchpoints in GDB. So ..
+ * we wake it up and hope that all is well.
+ */
+ ubc_wakeup();
+#endif
+
paging_init();
}
=20
diff -x CVS -urN linux-sh-head.orig/arch/sh/kernel/ubc.S linux-sh-head/arch=
/sh/kernel/ubc.S
--- linux-sh-head.orig/arch/sh/kernel/ubc.S Wed Dec 31 19:00:00 1969
+++ linux-sh-head/arch/sh/kernel/ubc.S Thu May 23 11:59:33 2002
@@ -0,0 +1,53 @@
+/*
+ * arch/sh/kernel/ubc.S
+ *
+ * Set of management routines for the User Break Controller (UBC)
+ *
+ * Copyright (C) 2002 Paul Mundt
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <linux/linkage.h>
+#include <asm/ubc.h>
+
+#define STBCR2 0xffc00010
+
+ENTRY(ubc_sleep)
+ mov #0, r0
+
+ mov.l 1f, r1 ! Zero out UBC_BBRA ..
+ mov.w r0, @r1
+
+ mov.l 2f, r1 ! .. same for BBRB ..
+ mov.w r0, @r1
+
+ mov.l 3f, r1 ! .. and again for BRCR.
+ mov.w r0, @r1
+
+ mov.w @r1, r0 ! Dummy read BRCR
+
+ mov.l 4f, r1 ! Set MSTP5 in STBCR2
+ mov.b @r1, r0
+ or #0x01, r0
+ mov.b r0, @r1
+
+ mov.b @r1, r0 ! Two dummy reads ..
+ mov.b @r1, r0
+
+ENTRY(ubc_wakeup)
+ mov.l 4f, r1 ! Clear MSTP5
+ mov.b @r1, r0
+ and #0xfe, r0
+ mov.b r0, @r1
+
+ mov.b @r1, r0 ! Two more dummy reads ..
+ mov.b @r1, r0
+
+1: .long UBC_BBRA
+2: .long UBC_BBRB
+3: .long UBC_BRCR
+4: .long STBCR2
+
diff -x CVS -urN linux-sh-head.orig/include/asm-sh/ptrace.h linux-sh-head/i=
nclude/asm-sh/ptrace.h
--- linux-sh-head.orig/include/asm-sh/ptrace.h Thu Mar 28 19:02:04 2002
+++ linux-sh-head/include/asm-sh/ptrace.h Thu May 23 11:30:06 2002
@@ -2,6 +2,7 @@
#define __ASM_SH_PTRACE_H
=20
#include <asm/processor.h>
+#include <asm/ubc.h>
=20
/*
* Copyright (C) 1999, 2000 Niibe Yutaka
@@ -68,68 +69,6 @@
#define user_mode(regs) (((regs)->sr & 0x40000000)=3D=3D0)
#define instruction_pointer(regs) ((regs)->pc)
extern void show_regs(struct pt_regs *);
-
-/* User Break Controller */
-
-#if defined(CONFIG_CPU_SUBTYPE_SH7709)
-#define UBC_TYPE_SH7729 (cpu_data->type =3D=3D CPU_SH7729)
-#else
-#define UBC_TYPE_SH7729 0
-#endif
-
-#if defined(__sh3__)
-#define UBC_BARA 0xffffffb0
-#define UBC_BAMRA 0xffffffb4
-#define UBC_BBRA 0xffffffb8
-#define UBC_BASRA 0xffffffe4
-#define UBC_BARB 0xffffffa0
-#define UBC_BAMRB 0xffffffa4
-#define UBC_BBRB 0xffffffa8
-#define UBC_BASRB 0xffffffe8
-#define UBC_BDRB 0xffffff90
-#define UBC_BDMRB 0xffffff94
-#define UBC_BRCR 0xffffff98
-#elif defined(__SH4__)
-#define UBC_BARA 0xff200000
-#define UBC_BAMRA 0xff200004
-#define UBC_BBRA 0xff200008
-#define UBC_BASRA 0xff000014
-#define UBC_BARB 0xff20000c
-#define UBC_BAMRB 0xff200010
-#define UBC_BBRB 0xff200014
-#define UBC_BASRB 0xff000018
-#define UBC_BDRB 0xff200018
-#define UBC_BDMRB 0xff20001c
-#define UBC_BRCR 0xff200020
-#endif
-
-#define BAMR_ASID (1 << 2)
-#define BAMR_NONE 0
-#define BAMR_10 0x1
-#define BAMR_12 0x2
-#define BAMR_ALL 0x3
-#define BAMR_16 0x8
-#define BAMR_20 0x9
-
-#define BBR_INST (1 << 4)
-#define BBR_DATA (2 << 4)
-#define BBR_READ (1 << 2)
-#define BBR_WRITE (2 << 2)
-#define BBR_BYTE 0x1
-#define BBR_HALF 0x2
-#define BBR_LONG 0x3
-#define BBR_QUAD (1 << 6) /* SH7750 */
-#define BBR_CPU (1 << 6) /* SH7709A,SH7729 */
-#define BBR_DMA (2 << 6) /* SH7709A,SH7729 */
-
-#define BRCR_CMFA (1 << 15)
-#define BRCR_CMFB (1 << 14)
-#define BRCR_PCTE (1 << 11)
-#define BRCR_PCBA (1 << 10) /* 1: after execution */
-#define BRCR_DBEB (1 << 7)
-#define BRCR_PCBB (1 << 6)
-#define BRCR_SEQ (1 << 3)
-#define BRCR_UBDE (1 << 0)
#endif
=20
#endif /* __ASM_SH_PTRACE_H */
diff -x CVS -urN linux-sh-head.orig/include/asm-sh/ubc.h linux-sh-head/incl=
ude/asm-sh/ubc.h
--- linux-sh-head.orig/include/asm-sh/ubc.h Wed Dec 31 19:00:00 1969
+++ linux-sh-head/include/asm-sh/ubc.h Thu May 23 11:30:01 2002
@@ -0,0 +1,73 @@
+#ifndef __ASM_SH_UBC_H
+#define __ASM_SH_UBC_H
+
+/* User Break Controller */
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7709)
+#define UBC_TYPE_SH7729 (cpu_data->type =3D=3D CPU_SH7729)
+#else
+#define UBC_TYPE_SH7729 0
+#endif
+
+#if defined(__sh3__)
+#define UBC_BARA 0xffffffb0
+#define UBC_BAMRA 0xffffffb4
+#define UBC_BBRA 0xffffffb8
+#define UBC_BASRA 0xffffffe4
+#define UBC_BARB 0xffffffa0
+#define UBC_BAMRB 0xffffffa4
+#define UBC_BBRB 0xffffffa8
+#define UBC_BASRB 0xffffffe8
+#define UBC_BDRB 0xffffff90
+#define UBC_BDMRB 0xffffff94
+#define UBC_BRCR 0xffffff98
+#elif defined(__SH4__)
+#define UBC_BARA 0xff200000
+#define UBC_BAMRA 0xff200004
+#define UBC_BBRA 0xff200008
+#define UBC_BASRA 0xff000014
+#define UBC_BARB 0xff20000c
+#define UBC_BAMRB 0xff200010
+#define UBC_BBRB 0xff200014
+#define UBC_BASRB 0xff000018
+#define UBC_BDRB 0xff200018
+#define UBC_BDMRB 0xff20001c
+#define UBC_BRCR 0xff200020
+#endif
+
+#define BAMR_ASID (1 << 2)
+#define BAMR_NONE 0
+#define BAMR_10 0x1
+#define BAMR_12 0x2
+#define BAMR_ALL 0x3
+#define BAMR_16 0x8
+#define BAMR_20 0x9
+
+#define BBR_INST (1 << 4)
+#define BBR_DATA (2 << 4)
+#define BBR_READ (1 << 2)
+#define BBR_WRITE (2 << 2)
+#define BBR_BYTE 0x1
+#define BBR_HALF 0x2
+#define BBR_LONG 0x3
+#define BBR_QUAD (1 << 6) /* SH7750 */
+#define BBR_CPU (1 << 6) /* SH7709A,SH7729 */
+#define BBR_DMA (2 << 6) /* SH7709A,SH7729 */
+
+#define BRCR_CMFA (1 << 15)
+#define BRCR_CMFB (1 << 14)
+#define BRCR_PCTE (1 << 11)
+#define BRCR_PCBA (1 << 10) /* 1: after execution */
+#define BRCR_DBEB (1 << 7)
+#define BRCR_PCBB (1 << 6)
+#define BRCR_SEQ (1 << 3)
+#define BRCR_UBDE (1 << 0)
+
+#ifndef __ASSEMBLY__
+/* arch/sh/kernel/ubc.S */
+extern void ubc_wakeup(void);
+extern void ubc_sleep(void);
+#endif
+
+#endif /* __ASM_SH_UBC_H */
+
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