Re: [linuxsh-dev] cache handling

[SUGIOKA T. <su...@it...>]

At 10:44 02/04/25 +0900, NIIBE Yutaka <gn...@m1...> wrote:
>Umm... The patch need some explanation.
>
>SUGIOKA Toshinobu wrote:
> > (1) If we use P1 address while accessing Cache Address Array, we can use 
>ASSOC
> >     bit without UTLB entry.
>
>This is cool thing.  I haven't thought it were mistake.
>This is a nice hack.  Here our intention is flushing a cache entry of
>matching physicall address.  Using ASSOC bit is basically for the
>use of U0 or P3 thing, but here we use it for P1 address to match
>physicall address.   I think that this is _not_ normal use
>somewhat crazy :-) use of ASSOC bit, isn't it?
>

I just guessed that address translation mechanism should be same as other
operations. According to my experiment, there is no problem on my SH7750 board. 

> > (2) For flushing O-cache entry, we can use movca.l/ocbi pair while BL 
>bit is set.
> >     This sequence can be executed in P1 area and does not cause any 
>unnecessary bus cycles.
>
>I don't know well about this.  Why/How those are different with ocbp?
>Do you have any reference?

The data written by "movca.l r0,@rn" here is just a garbage, so it should not be
written back to real memory. "ocbi" is better because it does not cause write back
cycle, and no extra address space is needed for writing garbage data.
I used 16kB aligned block which include empty_zero_page for this purpose. If garbage were
written into this area, kernel would crash immediately :P.

I have no reference about these things. I only happened to think and experimented.
So other guys confirmation may be required.

I'll commit this to 2.5.x trunk soon.

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SUGIOKA Toshinobu