[linuxsh-dev] cache handling

[NIIBE Y. <gn...@m1...>]

Umm... The patch need some explanation.

SUGIOKA Toshinobu wrote:
 > (1) If we use P1 address while accessing Cache Address Array, we can use ASSOC
 >     bit without UTLB entry.

This is cool thing.  I haven't thought it were mistake.
This is a nice hack.  Here our intention is flushing a cache entry of
matching physicall address.  Using ASSOC bit is basically for the
use of U0 or P3 thing, but here we use it for P1 address to match
physicall address.   I think that this is _not_ normal use
somewhat crazy :-) use of ASSOC bit, isn't it?

 > (2) For flushing O-cache entry, we can use movca.l/ocbi pair while BL bit is set.
 >     This sequence can be executed in P1 area and does not cause any unnecessary bus cycles.

I don't know well about this.  Why/How those are different with ocbp?
Do you have any reference?
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