Re: [linuxsh-dev] cache-sh4.c

[David M. <dav...@st...>]

gn...@m1... wrote:
> 
> Thanks for the testing.  Umm... I've read the hardware manual of SH7750 and
> SH7751.  I couldn't find the difference wrt the description of P2 requirement
> of cache handling.  I'll test this with SH7751 SolutionEngine.
> 

Niibe-san,
	It is in chapter 4 of the hardware manual, section 4.5  
"Memory-mapped Cache Configuration". It says "the OC content can be read
and 
written by a P1 and P2 area program ......".

> IIRC, Takashi Yoshii also has mentioned this.  I'm not sure if it's
> future plan or actual implementation, though.
>

I believe it is implementation.
 
> David, I'd like to confirm.  Is it OK for ST40STB1?

Yup, the ST40 is based on the later core version, so it should be fine.

-- 
Dave McKay 
Software Engineer STMicroelectronics
Email: dav...@st...