RE: [linuxsh-dev] cache-sh4.c

[NIIBE Y. <gn...@m1...>]

Here's the change.

2002-04-01  NIIBE Yutaka  <gn...@m1...>

	* arch/sh/mm/cache-sh4.c (flush_cache_4096_all, flush_cache_4096):
	Changed the compile time condition for ST40.  SH7751 needs to
	be P2 when handling cache.

	* arch/sh/mm/clear_page.S (__flush_cache_4096_all): Renamed
	from __flush_cache_4096_nocheck.

Index: arch/sh/mm/cache-sh4.c
===================================================================
RCS file: /cvsroot/linuxsh/linux/arch/sh/mm/cache-sh4.c,v
retrieving revision 1.10
diff -u -3 -p -r1.10 cache-sh4.c
--- arch/sh/mm/cache-sh4.c	1 Apr 2002 01:29:43 -0000	1.10
+++ arch/sh/mm/cache-sh4.c	1 Apr 2002 01:55:09 -0000
@@ -208,37 +208,48 @@ void flush_cache_sigtramp(unsigned long 
 	restore_flags(flags);
 }
 
-static void flush_cache_4096_nocheck(unsigned long start)
+static void flush_cache_4096_all(unsigned long start)
 {
-#if defined(CONFIG_CPU_SUBTYPE_SH7750)
+#if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
+	/*
+	 * ST40 have no restriction to handle cache.
+	 * (While SH7750/SH7751 must do that at P2 area.)
+	 */
+	unsigned long addr;
+	for (addr = start; addr < start + 4096; addr += 32)
+		ctrl_outl(0, addr);
+#else
 	register unsigned long __r0 __asm__ ("r0") = 0;
 	register unsigned long __r1 __asm__ ("r1") = 128;
 	register unsigned long __r4 __asm__ ("r4");
 	register unsigned long __r5 __asm__ ("r5");
 	register unsigned long __r6 __asm__ ("r6");
 	register unsigned long __r7 __asm__ ("r7");
-	extern void __flush_cache_4096_nocheck(unsigned long);
+	extern void __flush_cache_4096_all(unsigned long);
 
 	asm volatile("jsr	@%7; nop"
 		     : "=&r" (__r4), "=&r" (__r5), "=&r" (__r6), "=&r" (__r7)
 		     : "0" (start), "r" (__r0), "r" (__r1), 
-		       "r" (__flush_cache_4096_nocheck + 0x20000000)
+		       "r" (__flush_cache_4096_all + 0x20000000)
 		     : "pr");
-#else
-	/*
-	 * SH7751 and ST40 have no restriction to handle cache.
-	 * (While SH7750 must do that at P2 area.)
-	 */
-	unsigned long addr;
-	for (addr = start; addr < start + 4096; addr += 32)
-		ctrl_outl(0, addr);
 #endif
 }
 
 static inline void flush_cache_4096(unsigned long start,
 				    unsigned long phys)
 {
-#if defined(CONFIG_CPU_SUBTYPE_SH7750)
+#if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
+	/*
+	 * ST40 have no restriction to handle cache.
+	 * (While SH7750/SH7751 must do that at P2 area.)
+	 */
+	unsigned long addr, data;
+	for (addr = start; addr < start + 4096; addr += 32) {
+		data = ctrl_inl(addr)&(0x1ffff000|CACHE_VALID);
+		if (data == phys)
+			ctrl_outl(0, addr);
+	}
+#else
 	register unsigned long addr __asm__ ("r4");
 	register unsigned long data __asm__ ("r0");
 	register unsigned long __r5 __asm__ ("r5") = phys;
@@ -251,17 +262,6 @@ static inline void flush_cache_4096(unsi
 		     : "0" (start), "1" (__flush_cache_4096 + 0x20000000), 
 		       "r" (__r5), "r" (__r6), "r" (__r7)
 		     : "pr");
-#else
-	/*
-	 * SH7751 and ST40 have no restriction to handle cache.
-	 * (While SH7750 must do that at P2 area.)
-	 */
-	unsigned long addr, data;
-	for (addr = start; addr < start + 4096; addr += 32) {
-		data = ctrl_inl(addr)&(0x1ffff000|CACHE_VALID);
-		if (data == phys)
-			ctrl_outl(0, addr);
-	}
 #endif
 }
 
@@ -301,13 +301,15 @@ static inline void flush_icache_all(void
 	restore_flags(flags);
 }
 
+#undef C_IMPLEMENTATION_OF_CACHE_ALL
+
 void flush_cache_all(void)
 {
 	extern unsigned long empty_zero_page[1024];
 
 	/* Prefetch the data to write back D-cache */
 
-#if C_IMPLEMENTATION
+#ifdef C_IMPLEMENTATION_OF_CACHE_ALL
 	unsigned long addr;
 
 	for (addr = (unsigned long)empty_zero_page;
@@ -435,13 +437,13 @@ void flush_cache_range(struct vm_area_st
 	} while (p < end);
  loop_exit:
 	if (d & 1)
-		flush_cache_4096_nocheck(CACHE_OC_ADDRESS_ARRAY);
+		flush_cache_4096_all(CACHE_OC_ADDRESS_ARRAY);
 	if (d & 2)
-		flush_cache_4096_nocheck(CACHE_OC_ADDRESS_ARRAY | 0x1000);
+		flush_cache_4096_all(CACHE_OC_ADDRESS_ARRAY | 0x1000);
 	if (d & 4)
-		flush_cache_4096_nocheck(CACHE_OC_ADDRESS_ARRAY | 0x2000);
+		flush_cache_4096_all(CACHE_OC_ADDRESS_ARRAY | 0x2000);
 	if (d & 8)
-		flush_cache_4096_nocheck(CACHE_OC_ADDRESS_ARRAY | 0x3000);
+		flush_cache_4096_all(CACHE_OC_ADDRESS_ARRAY | 0x3000);
 	if (vma->vm_flags & VM_EXEC)
 		flush_icache_all();
 }
Index: arch/sh/mm/clear_page.S
===================================================================
RCS file: /cvsroot/linuxsh/linux/arch/sh/mm/clear_page.S,v
retrieving revision 1.4
diff -u -3 -p -r1.4 clear_page.S
--- arch/sh/mm/clear_page.S	1 Apr 2002 01:29:43 -0000	1.4
+++ arch/sh/mm/clear_page.S	1 Apr 2002 01:55:09 -0000
@@ -182,7 +182,7 @@ ENTRY(__clear_user_page)
 	 nop
 .L4096:	.word	4096
 
-#if defined(CONFIG_CPU_SUBTYPE_SH7750)
+#if !defined(CONFIG_CPU_SUBTYPE_ST40STB1) /* SH7750 or SH7751 */
 ENTRY(__flush_cache_4096)
 	.rept	128
 	mov.l	@r4,r0
@@ -202,7 +202,7 @@ ENTRY(__flush_cache_4096)
 	rts
 	 nop
 
-ENTRY(__flush_cache_4096_nocheck)
+ENTRY(__flush_cache_4096_all)
 	mov	r4,r5
 	mov	r4,r6
 	mov	r4,r7
Index: arch/sh/mm/copy_page.S
===================================================================
RCS file: /cvsroot/linuxsh/linux/arch/sh/mm/copy_page.S,v
retrieving revision 1.2
diff -u -3 -p -r1.2 copy_page.S
--- arch/sh/mm/copy_page.S	27 Mar 2002 09:30:48 -0000	1.2
+++ arch/sh/mm/copy_page.S	1 Apr 2002 01:55:09 -0000
@@ -84,7 +84,6 @@ ENTRY(copy_page)
  * r10 --- to
  * r11 --- from
  */
-#include <linux/linkage.h>
 ENTRY(__copy_user_page)
 	mov.l	r8,@-r15
 	mov.l	r9,@-r15