Re: [linuxsh-dev] cache-sh4.c

[NIIBE Y. <gn...@m1...>]

David McKay wrote:
 > Niibe-san,
 > 	One of the differences between the 7750 and 7751 (and ST40) processors
 > is that the restriction to flush D-cache from P2 only has been lifted.

Excellent!  I didn't know that.

If I could suggest more feature, I think it would be great that if we
had a feature of flushing cache of physcal address (page), so that we
don't need to loop all the cache, in the first place.

The change I've made works well for 7750 (in P2).  With instruction
cache enabled (P1), I think that loop works better.
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