Re: [linuxsh-dev] cache-sh4.c

[David M. <dav...@st...>]

gn...@m1... wrote:
> 
> Optimized the flushing.
> 
> There is a requirement in SH4 to control cache from P2 area.  P2 area
> is the area where cache is not used at all.  This means, the cycles
> for instruction could be quite large.  In other word, if we could
> save number of instructions, we see performance improvement.
> 


Niibe-san,
	One of the differences between the 7750 and 7751 (and ST40) processors
is that the restriction to flush D-cache from P2 only has been lifted.
This does
provide a significant performance increase. We did spend a while trying
to find out
if this was a documentation change or a real change, but as far as we
can tell it does
appear to be a genuine change in the core.  I ran a modified kernel and
saw no problems 
not doing the change to P2.  You have to read the manual really
carefully to realise it has
changed!


-- 
Dave McKay 
Software Engineer STMicroelectronics
Email: dav...@st...