Re: [linuxsh-dev] Slight cleanup of CCR definitions.

[David W. <dw...@in...>]

gn...@m1... said:
>  Looks good.  If possible, please sync -sh4.c too.

/me digs out some SH4 docs.... OK. Untested but "Obviously Correct(tm)".

Index: ChangeLog
===================================================================
RCS file: /cvsroot/linuxsh/kernel/ChangeLog,v
retrieving revision 1.339
diff -u -r1.339 ChangeLog
--- ChangeLog	2001/09/10 08:59:59	1.339
+++ ChangeLog	2001/09/10 11:03:57
@@ -2,6 +2,7 @@
 
 	* arch/sh/mm/cache-sh3.c: Clearer definitions of CCR_CACHE_VAL and
 	CCR_CACHE_INIT.
+	* arch/sh/mm/cache-sh4.c: Likewise.
 
 2001-09-03  NIIBE Yutaka  <gn...@m1...>
 
Index: arch/sh/mm/cache-sh4.c
===================================================================
RCS file: /cvsroot/linuxsh/kernel/arch/sh/mm/cache-sh4.c,v
retrieving revision 1.15
diff -u -r1.15 cache-sh4.c
--- arch/sh/mm/cache-sh4.c	2001/08/10 14:13:13	1.15
+++ arch/sh/mm/cache-sh4.c	2001/09/10 11:03:57
@@ -22,9 +22,21 @@
 #include <asm/mmu_context.h>
 
 #define CCR		 0xff00001c	/* Address of Cache Control Register */
-#define CCR_CACHE_VAL	 0x00000105	/* 8k+16k-byte cache,P1-wb,enable */
-#define CCR_CACHE_INIT	 0x0000090d	/* ICI,ICE(8k), OCI,P1-wb,OCE(16k) */
-#define CCR_CACHE_ENABLE 0x00000101
+
+#define CCR_CACHE_OCE	0x0001	/* Operand Cache Enable */
+#define CCR_CACHE_WT	0x0002	/* Write-Through (for P0,U0,P3) (else writeback)*/
+#define CCR_CACHE_CB	0x0004	/* Copy-Back (for P1) (else writethrough) */
+#define CCR_CACHE_OCI	0x0008	/* OC Invalidate */
+#define CCR_CACHE_ORA	0x0020	/* OC RAM Mode */
+#define CCR_CACHE_OIX	0x0080	/* OC Index Enable */
+#define CCR_CACHE_ICE	0x0100	/* Instruction Cache Enable */
+#define CCR_CACHE_ICI	0x0800	/* IC Invalidate */
+#define CCR_CACHE_IIX	0x8000	/* IC Index Enable */
+
+/* Default CCR setup: 8k+16k-byte cache,P1-wb,enable */
+#define CCR_CACHE_VAL	(CCR_CACHE_ICE|CCR_CACHE_CB|CCR_CACHE_OCE)
+#define CCR_CACHE_INIT	(CCR_CACHE_VAL|CCR_CACHE_OCI|CCR_CACHE_ICI)
+#define CCR_CACHE_ENABLE (CCR_CACHE_OCE|CCR_CACHE_ICE)
 
 #define CACHE_IC_ADDRESS_ARRAY 0xf0000000
 #define CACHE_OC_ADDRESS_ARRAY 0xf4000000

--
dwmw2