Re: [linuxsh-dev] SH-4 cache problem?

[SUGIOKA T. <su...@it...>]

At 17:32 01/08/07 +0900, NIIBE Yutaka <gn...@m1...> wrote:
>Here's the patch (for me, this is work around).  Please try.  It works
>for my environment.
>
>	* arch/sh/mm/fault.c (update_mmu_cache): Flush the cache when first
>	mapped, even if it has no alias.  We need this to use NFS.
>

Yes. it works with your patch. but performance seems went bad.
I think unneeded cache flush occur on simple TLB miss exception.

Following patch improves 'exec' system call performance much on my NFS environment.

	* arch/sh/mm/fault.c (__do_page_fault): Don't call update_mmu_cache().

Index: arch/sh/mm/fault.c
===================================================================
RCS file: /cvsroot/linuxsh/kernel/arch/sh/mm/fault.c,v
retrieving revision 1.45
diff -u -r1.45 fault.c
--- arch/sh/mm/fault.c  2001/08/07 05:20:02     1.45
+++ arch/sh/mm/fault.c  2001/08/07 09:42:03
@@ -237,6 +237,7 @@
        pmd_t *pmd;
        pte_t *pte;
        pte_t entry;
+       unsigned long pteval;

        if (address >= P3SEG && address < P4SEG)
                dir = pgd_offset_k(address);
@@ -270,7 +271,24 @@
        __flush_tlb_page(get_asid(), address&PAGE_MASK);
 #endif
        set_pte(pte, entry);
-       update_mmu_cache(NULL, address, entry);
+
+       /* Set PTEH register */
+       ctrl_outl((address & MMU_VPN_MASK) | get_asid(), MMU_PTEH);
+
+       pteval = pte_val(entry);
+#if defined(__SH4__)
+       /* Set PTEA register */
+       /* TODO: make this look less hacky */
+       ctrl_outl(((pteval >> 28) & 0xe) | (pteval & 0x1), MMU_PTEA);
+#endif
+
+       /* Set PTEL register */
+       pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
+       /* conveniently, we want all the software flags to be 0 anyway */
+       ctrl_outl(pteval, MMU_PTEL);
+
+       /* Load the TLB */
+       asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
        return 0;
 }


----
SUGIOKA Toshinobu