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[linuxsh-dev] sh-ipl+g change
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From: Masahiro A. <m-...@aa...> - 2001-07-20 08:44:02
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Hello all. Today I'm posting the patch to sh-ipl+g (hosted on cvs.m17n.org, not on SourceForge). Patch includes those: * ADX (our custom board) support * Auto-boot from IDE/CF. Generalized the idea introduced for cat68701 and sh2000 board. * No output to serial supported. Last two features can be configured in config/config.h-xxx file for each board's needs. Please note that this patch is to be applied to the source hosted on cvs.m17n.org. You can access it like this. To Login: (no password) cvs -d :pserver:ano...@cv...:/cvs/superh login To Checkout: cvs -d :pserver:ano...@cv...:/cvs/superh co ipl+g You can also get lilo from this server. It supports self-lilo and understands "append=" sentence in lilo.conf. To checkout, cvs -d :pserver:ano...@cv...:/cvs/superh co lilo Here is the patch. I appreciate your input. --- diff -ruN -X ipldontdiff cvsroot/m17n/ipl+g/ChangeLog /sh4/usr/src/ipl+g/ChangeLog --- cvsroot/m17n/ipl+g/ChangeLog Wed Jul 18 11:13:14 2001 +++ /sh4/usr/src/ipl+g/ChangeLog Fri Jul 20 16:42:10 2001 @@ -1,3 +1,14 @@ +2001-07-20 Masahiro ABE <m-...@aa...> + + * config/{config.h-adx,config.h-adx-scif,config.mk-adx} : New file. + * config/config.h-cat68701 : Added CONFIG_AUTO_BOOT_IDE. + (CONFIG_ROM_START, CONFIG_ROM_LENGTH, CONFIG_RAM_START, + CONFIG_RAM_BOOT): Defined. + * Makefile : Added CONFIG_ADX. + * defs.h : Added general IDE Auto-booting feature support. + * main.c (start_main): make Auto-boot code usable for other board. + * sh-sci.c : Do nothing if both CONFIG_SCI/SCIF not defined. + 2001-07-02 SUGIOKA Toshinobu <su...@it...> * cs89x0.c (detect_tp): Change cable detection timeout to diff -ruN -X ipldontdiff cvsroot/m17n/ipl+g/Makefile /sh4/usr/src/ipl+g/Makefile --- cvsroot/m17n/ipl+g/Makefile Wed Jun 20 11:30:16 2001 +++ /sh4/usr/src/ipl+g/Makefile Thu Jul 19 14:23:49 2001 @@ -182,6 +182,15 @@ # ADJUST_VMA=0x00000000 endif +ifdef CONFIG_ADX +MACHINE_DEPENDS := init-adx.o +# 0x00000000(address for ROM image)-0xa0000000(final destination) = 0x60000000 +ADJUST_VMA=0x60000000 + +sh-stub.srec: sh-stub.exe + $(OBJCOPY) -S -R .data -R .stack -R .bss -R .comment \ + -O srec sh-stub.exe sh-stub.srec +endif ifdef CONFIG_IDE MACHINE_DEPENDS += ide.o diff -ruN -X ipldontdiff cvsroot/m17n/ipl+g/config/config.h-adx /sh4/usr/src/ipl+g/config/config.h-adx --- cvsroot/m17n/ipl+g/config/config.h-adx Thu Jan 1 09:00:00 1970 +++ /sh4/usr/src/ipl+g/config/config.h-adx Fri Jul 20 15:53:08 2001 @@ -0,0 +1,12 @@ +#define CONFIG_LITTLE_ENDIAN 1 +#define CONFIG_ADX 1 +#define CONFIG_IDE 1 +#define CONFIG_ROM_START 0x80000000 +#define CONFIG_ROM_LENGTH 0x80000 +#define CONFIG_RAM_START 0x88000000 +#define CONFIG_RAM_BOOT (CONFIG_RAM_START+0x200000) +#define CONFIG_MEMORY_SIZE 0x02000000 +#define CONFIG_DIRECT_COMPACT_FLASH 1 +#define CONFIG_CIS_BASE 0xb4000000 +#define CONFIG_IO_BASE 0xb6000000 +#define CONFIG_AUTO_BOOT_IDE 1 diff -ruN -X ipldontdiff cvsroot/m17n/ipl+g/config/config.h-adx-scif /sh4/usr/src/ipl+g/config/config.h-adx-scif --- cvsroot/m17n/ipl+g/config/config.h-adx-scif Thu Jan 1 09:00:00 1970 +++ /sh4/usr/src/ipl+g/config/config.h-adx-scif Fri Jul 20 15:54:07 2001 @@ -0,0 +1,3 @@ +#include "config/config.h-adx" + +#define CONFIG_SCIF 1 diff -ruN -X ipldontdiff cvsroot/m17n/ipl+g/config/config.h-cat68701 /sh4/usr/src/ipl+g/config/config.h-cat68701 --- cvsroot/m17n/ipl+g/config/config.h-cat68701 Mon Jun 4 18:09:20 2001 +++ /sh4/usr/src/ipl+g/config/config.h-cat68701 Fri Jul 20 16:33:45 2001 @@ -2,9 +2,13 @@ #define CONFIG_CAT68701 1 #define CONFIG_SCI 1 #define CONFIG_IDE 1 -#define CONFIG_RAM_BOOT 0x8c200000 #define CONFIG_DIRECT_COMPACT_FLASH 1 +#define CONFIG_ROM_START 0x80000000 +#define CONFIG_ROM_LENGTH 0x8000 +#define CONFIG_RAM_START 0x8c000000 +#define CONFIG_RAM_BOOT (CONFIG_RAM_START+0x200000) #define CONFIG_IO_BASE 0xba000000 #define CONFIG_MEMORY_SIZE 0x01000000 #define CONFIG_CIS_BASE 0xb8000000 +#define CONFIG_AUTO_BOOT_IDE 1 diff -ruN -X ipldontdiff cvsroot/m17n/ipl+g/config/config.mk-adx /sh4/usr/src/ipl+g/config/config.mk-adx --- cvsroot/m17n/ipl+g/config/config.mk-adx Thu Jan 1 09:00:00 1970 +++ /sh4/usr/src/ipl+g/config/config.mk-adx Tue Jun 12 11:57:00 2001 @@ -0,0 +1,4 @@ +CONFIG_LITTLE_ENDIAN=y +CONFIG_CPU_SH4=y +CONFIG_ADX=y +CONFIG_IDE=y diff -ruN -X ipldontdiff cvsroot/m17n/ipl+g/defs.h /sh4/usr/src/ipl+g/defs.h --- cvsroot/m17n/ipl+g/defs.h Fri Jun 29 22:44:47 2001 +++ /sh4/usr/src/ipl+g/defs.h Thu Jul 19 14:01:00 2001 @@ -85,3 +85,13 @@ extern void pci_write_config_dword (unsigned long offset, unsigned long data); extern unsigned long pci_nextio, pci_nextmem; #endif + +/* Auto-boot support */ +#if defined(CONFIG_AUTO_BOOT_IDE) +# if defined(CONFIG_CAT68701) +extern int cat68701_read_dipsw(void); +# define AUTO_BOOT_IDE_CHECK (!(cat68701_read_dipsw () &1)) +# else +# define AUTO_BOOT_IDE_CHECK (1) +# endif +#endif /* defined(CONFIG_AUTO_BOOT_IDE) */ diff -ruN -X ipldontdiff cvsroot/m17n/ipl+g/init-adx.S /sh4/usr/src/ipl+g/init-adx.S --- cvsroot/m17n/ipl+g/init-adx.S Thu Jan 1 09:00:00 1970 +++ /sh4/usr/src/ipl+g/init-adx.S Wed Jul 18 21:57:13 2001 @@ -0,0 +1,237 @@ +/* + * + * sh-ipl+g/init-adx.S + * (based on sh-ipl+g/init-sesh4.S, init-sh2000.S and init-cat68701.S) + * + */ + +#include "config.h" +#include "linkage.h" + +ENTRY(init_bsc) + + /* Setup WDT for FRQCR change */ + mov.l WTCSR_A,r1 /* WTCSR Address */ + mov.w WTCSR_D,r0 /* WTCSR Data (WDT Disable) */ + mov.w r0,@r1 + + mov.l WTCNT_A,r1 /* WTCNT Address */ + mov.w WTCNT_D,r0 /* WTCNT Data (WDT overflows after 5.25msec) */ + mov.w r0,@r1 + + mov.l FRQCR_A,r1 /* FRQCR Address */ + mov.l FRQCR_D,r0 /* FRQCR Data */ + mov.w r0,@r1 + /* Here the clock stops until watchdog timer overflow*/ + + mov.l BCR1_A,r1 /* BCR1 Address */ + mov.l BCR1_D,r0 /* BCR1 Data */ + mov.l r0,@r1 + + mov.l BCR2_A,r1 /* BCR2 Address */ + mov.l BCR2_D,r0 /* BCR2 Data */ + mov.w r0,@r1 + + mov.l WCR1_A,r1 /* WCR1 Address */ + mov.l WCR1_D,r0 /* WCR1 Data */ + mov.l r0,@r1 + + mov.l WCR2_A,r1 /* WCR2 Address */ + mov.l WCR2_D,r0 /* WCR2 Data */ + mov.l r0,@r1 + + mov.l WCR3_A,r1 /* WCR3 Address */ + mov.l WCR3_D,r0 /* WCR3 Data */ + mov.l r0,@r1 + + mov.l MCR_A,r1 /* MCR Address */ + mov.l MCR_D1,r0 /* MCR Data1 */ + mov.l r0,@r1 + + mov.l SDMR3_A,r1 /* Set SDRAM mode */ + mov #0,r0 + mov.b r0,@r1 + + ! Do you need PCMCIA setting? + ! If so, please add the lines here... + + mov.l RTCNT_A,r1 /* RTCNT Address */ + mov.l RTCNT_D,r0 /* RTCNT Data */ + mov.w r0,@r1 + + mov.l RTCOR_A,r1 /* RTCOR Address */ + mov.l RTCOR_D,r0 /* RTCOR Data */ + mov.w r0,@r1 + + mov.l RTCSR_A,r1 /* RTCSR Address */ + mov.l RTCSR_D,r0 /* RTCSR Data */ + mov.w r0,@r1 + + mov.l RFCR_A,r1 /* RFCR Address */ + mov.l RFCR_D,r0 /* RFCR Data */ + mov.w r0,@r1 /* Clear reflesh counter */ + + /* Wait DRAM refresh 30 times */ + mov #30,r3 +1: + mov.w @r1,r0 + extu.w r0,r2 + cmp/hi r3,r2 + bf 1b + + mov.l MCR_A,r1 /* MCR Address */ + mov.l MCR_D2,r0 /* MCR Data2 */ + mov.l r0,@r1 + + mov.l SDMR3_A,r1 /* Set SDRAM mode */ + mov #0,r0 + mov.b r0,@r1 + +/* Configure & Reset Compact flash */ +#if defined(CONFIG_DIRECT_COMPACT_FLASH) && defined(CONFIG_IDE) + /* wait until power on reset complete */ + mov.l DLY_CNT,r0 +2: dt r0 + bf 2b + + /* setup PTEA for 16bit attibute access */ + mov.l PTEA_A,r1 /* PTEA Address */ + mov.l PTEA_D_ATR,r0 /* 16bit attribute area */ + mov.l r0,@r1 + + /* soft reset */ + mov.l CF_COR_A, r1 + mov #0x80, r0 + mov.w r0, @r1 + + /* put some wait */ + mov.l DLY_CNT2,r0 +2: dt r0 + bf 2b + + /* soft reset clear */ + mov.l CF_COR_A, r1 + mov #0x00, r0 + mov.w r0, @r1 + + mov.l CF_PRR_A,r1 /* wait until RRdy/Busy clear */ +2: mov.w @r1,r0 + and #2,r0 + tst r0,r0 + bt 2b + + mov.l CF_CCSR_A,r1 /* Powerdown mode bit clear */ + mov #0,r0 + mov.w r0,@r1 + + mov.l CF_PRR_A,r1 /* wait until RRdy/Busy clear */ +2: mov.w @r1,r0 + and #2,r0 + tst r0,r0 + bt 2b + + /* Select configuration: 0x02, Level interrupt: 0x40 */ + mov.l CF_COR_A, r1 + mov #0x42, r0 + mov.w r0, @r1 + + mov.l CF_PRR_A,r1 /* wait until RRdy/Busy clear */ +2: + mov.w @r1,r0 + and #2,r0 + tst r0,r0 + bt 2b + + /* setup PTEA for 16bit I/O access */ + mov.l PTEA_A,r1 /* PTEA Address */ + mov.l PTEA_D_IO,r0 /* 16bit I/O area */ + mov.l r0,@r1 +#endif + + rts + nop + + .align 2 + +WTCNT_A: + .long 0xffc00008 /* WDT CNT */ +WTCNT_D: + .word 0x5a00 /* initial counter value, with magic byte "5a" */ +WTCSR_A: + .long 0xffc0000c /* WDT CSR */ +WTCSR_D: + .word 0xa507 /* TME = 0, CKS=7, with magic byte "a5" */ +FRQCR_A: + .long 0xFFC00000 /* FRQCR Address */ +FRQCR_D: + .long 0x00000e13 /* 6:2:1 */ +BCR1_A: + .long 0xFF800000 /* BCR1 Address */ +BCR1_D: + .long 0x0000000d /* Area 2 & 3 SDRAM, Area 5 & 6 PCMCIA */ +BCR2_A: + .long 0xFF800004 /* BCR2 Address */ +BCR2_D: + .long 0x1B08 /* Area 1:16bit Area 2:64bit Area 3:64bit + Area 4:32bit Area 5:16bit Area 6:8bit */ +WCR1_A: + .long 0xFF800008 /* WCR1 Address */ +WCR1_D: + .long 0x02720077 /* Device-inter-cycle: 2-wait + A6:15 A5:2 A4:2 A3:0 A2:0 A1:15 A0:15 */ +WCR2_A: + .long 0xFF80000C /* WCR2 Address */ +WCR2_D: + .long 0xFFFE44BF /* A6: 15 A6B: 7 A5: 15 A5B: 7 + A4: 15 A3: 2 A2:15 A1:15 A0:15 A0B:7 */ +WCR3_A: + .long 0xFF800010 /* WCR3 Address */ +WCR3_D: + .long 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3 + A2: 1-3 A1: 1-3 A0: 0-1 */ +RTCNT_A: + .long 0xFF800020 /* RTCNT Address */ +RTCNT_D: + .long 0xA500 /* RTCNT Write Code A5h Data 00h */ + +RTCOR_A: + .long 0xFF800024 /* RTCOR Address */ +RTCOR_D: + .long 0xA510 /* RTCOR Write Code A5h Data 10h (15us) */ + +RTCSR_A: + .long 0xFF80001C /* RTCSR Address */ +RTCSR_D: + .long 0xA518 /* RTCSR Write Code A5h Data 18h */ + +SDMR3_A: + .long 0xFF900110 /* SDMR2 Address */ +MCR_A: + .long 0xFF800014 /* MCR Address */ +MCR_D1: + .long 0x50110014 /* MRSET:'0' */ +MCR_D2: + .long 0x10110014 /* MRSET:'1' */ +RFCR_A: + .long 0xFF800028 /* RFCR Address */ +RFCR_D: + .long 0xA400 /* RFCR Write Code A4h Data 00h */ +#if defined(CONFIG_DIRECT_COMPACT_FLASH) && defined(CONFIG_IDE) +PTEA_A: .long 0xFF000034 /* PTEA Address */ +PTEA_D_IO: + .long 0x00000003 /* SA0-2: 16bit I/O area */ +PTEA_D_MEM: + .long 0x00000005 /* SA0-2: 16bit common memory */ +PTEA_D_ATR: + .long 0x00000007 /* SA0-2: 16bit attribute area */ +DLY_CNT: + .long 80000 +DLY_CNT2: + .long 8000 +CF_COR_A: + .long (CONFIG_CIS_BASE+0x0200) +CF_CCSR_A: + .long (CONFIG_CIS_BASE+0x0202) +CF_PRR_A: + .long (CONFIG_CIS_BASE+0x0204) +#endif diff -ruN -X ipldontdiff cvsroot/m17n/ipl+g/main.c /sh4/usr/src/ipl+g/main.c --- cvsroot/m17n/ipl+g/main.c Fri Jun 29 22:44:47 2001 +++ /sh4/usr/src/ipl+g/main.c Fri Jul 20 16:08:10 2001 @@ -178,15 +178,17 @@ #endif } -#ifdef CONFIG_CAT68701 - if (get_boot_signature () != 0xdeadbeef && !(cat68701_read_dipsw () &1)) + if (get_boot_signature () != 0xdeadbeef) { - ide_detect_devices (); - sti (); - ide_startup_devices (); - boot (); - } +#if defined(CONFIG_AUTO_BOOT_IDE) + if (AUTO_BOOT_IDE_CHECK && (ide_detect_devices () == 0)) + { + sti (); + ide_startup_devices (); + boot (); + } #endif + } #ifdef CONFIG_SH2000 if (get_boot_signature () != 0xdeadbeef) diff -ruN -X ipldontdiff cvsroot/m17n/ipl+g/sh-sci.c /sh4/usr/src/ipl+g/sh-sci.c --- cvsroot/m17n/ipl+g/sh-sci.c Wed Jun 6 21:29:07 2001 +++ /sh4/usr/src/ipl+g/sh-sci.c Fri Jul 20 15:41:44 2001 @@ -15,6 +15,9 @@ #include "config.h" #include "io.h" +#if (defined(CONFIG_SCI) || defined(CONFIG_SCIF)) +/* with serial-console */ + #if defined(CONFIG_SCI) #define SCSCR_INIT 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ #if defined(__sh3__) @@ -297,3 +300,40 @@ putDebugChar (*p); } } + +#else /*if (defined(CONFIG_SCI) || defined(CONFIG_SCIF))*/ +/* without serial-console */ + +void +handleError (void) +{ +} + +void +init_serial(void) +{ +} + +int +getDebugCharTimeout (int count) +{ + return 0; +} + +char +getDebugChar (void) +{ + return 0; +} + +void +putDebugChar (char ch) +{ +} + +void +putString (char *str) +{ +} + +#endif /*if (defined(CONFIG_SCI) || defined(CONFIG_SCIF))*/ --- ================================= Masahiro ABE, A&D Co., Ltd. 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