Re: [linuxsh-dev] SH-4 RTC

[Philipp R. <pr...@ma...>]

On Sun, 18 Feb 2001, NIIBE Yutaka wrote:
> While implementing RTC routine in SH IPL+g:
> --------------------------
> static unsigned long get_tick_1 (void)
> {
>   unsigned int cnt128, sec, min, hour;
> 
>   while (1)
>     {
>       p4_outb (RCR1, 0);  /* Clear CF-bit */
> 
>       cnt128 = (p4_inb (R64CNT) ^ RTC_BIT_CHANGE);
>       sec = p4_inb (RSECCNT);
>       min = p4_inb (RMINCNT);
>       hour = p4_inb (RHRCNT);
> 
>       if ((p4_inb (RCR1) & RCR1_CF) == 0)
>       break;
>     }
> 
>   BCD_TO_BIN(sec);
>   BCD_TO_BIN(min);
>   BCD_TO_BIN(hour);
> 
>   return cnt128 + 128*(sec+60*(min+60*hour));
> }
> --------------------------
> 
> I think I've found a hardware bug(? or feature) of SH-4.  I need to
> set RTC_BIT_CHANGE as 0x40, to get the straight value of the tick.
> Without this, the tick value goes backward(!) sometime.

This is bad.  I don't have access to my SuperH machine to test right now,
but I would suggest we stop using the 128 Hz register until we found a
reliable way to detect the chip bug.

> If it's true, we need to fix our RTC related code.  Could you please
> check your CPU?  How about chips by ST?

I think my CPU clock calibration code should work fine if you just delete
the code reading R64CNT.  I haven't checked the recent changes committed
to it though.