From: SUGIOKA T. <su...@it...> - 2000-12-02 15:09:42
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Hi, all. I'm using current cvs version of the kernel, and found that SH7709A(118MHz) executes user-land programs much faster than SH7750(200MHz). following patch makes this things better. my SH7750 board takes about 4.7sec when compile hello.c before applying this patch, and 2.2sec after patch. current __flush_page_to_ram invalidates data cache of the page, but I think write back is sufficient. I'm not sure whether this patch causes synonym problem. Is this approach correct ? Index: arch/sh/mm/cache.c =================================================================== RCS file: /cvsroot/linuxsh/kernel/arch/sh/mm/cache.c,v retrieving revision 1.21 diff -u -r1.21 cache.c --- arch/sh/mm/cache.c 2000/09/18 05:15:35 1.21 +++ arch/sh/mm/cache.c 2000/12/02 14:38:14 @@ -397,22 +397,21 @@ */ void __flush_page_to_ram(void *kaddr) { - unsigned long phys, addr, data, i; + unsigned long v; - /* Physical address of this page */ - phys = PHYSADDR(kaddr); - - jump_to_P2(); - /* Loop all the D-cache */ - for (i=0; i<CACHE_OC_NUM_ENTRIES; i++) { - addr = CACHE_OC_ADDRESS_ARRAY| (i<<CACHE_OC_ENTRY_SHIFT); - data = ctrl_inl(addr); - if ((data & CACHE_VALID) && (data&PAGE_MASK) == phys) { - data &= ~(CACHE_UPDATED|CACHE_VALID); - ctrl_outl(data, addr); - } + for (v = (unsigned long)kaddr; v < (unsigned long)kaddr+PAGE_SIZE; ) { + asm volatile( + "ocbwb @%0\n\t" + "add %2,%0\n\t" + "ocbwb @%0\n\t" + "add %2,%0\n\t" + "ocbwb @%0\n\t" + "add %2,%0\n\t" + "ocbwb @%0\n\t" + "add %2,%0\n\t" + : "=r"(v) + : "0" (v), "r"(L1_CACHE_BYTES)); } - back_to_P1(); } void flush_page_to_ram(struct page *pg) ----- SUGIOKA Toshinobu |