From: Greg B. <gb...@po...> - 2000-10-11 10:59:11
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G'day I've uploaded a new version of my HD64465 PCMCIA patch to sourceforge http://sourceforge.net/patch/download.php?id=101674 Niibe-san, I want to check if you're happy about an architectural aspect of my patch, which Peter Hung and I have been discussing. I've used the MMU to set up mappings for PCMCIA IO-space. My approach has been to use get_vm_area() to allocate a region of kernel-only VM, then setup mappings using remap_page_range() (i.e. like ioremap() does on x86). I've extended the PTE bits to encode the TC and SA bits needed for PCMCIA mappings, and extended the TLB miss handler to load the PTEA register by shifting and masking bits from the PTE. To supply TC&SA bits for PCMCIA mappings, a special pgprot_t value is constructed by the PCMCIA host bridge driver and passed to remap_page_range(). This means that PCMCIA IO-space mappings are loaded into the TLB in exactly the same way as other mappings. In particular, wired TLB entries are *not* used. But the downside is a small number of extra instructions in the main path for all TLB misses (PCMCIA and non-PCMCIA alike). My question is, is this approach acceptable? Is the performance hit in the TLB miss handler worth freeing up the TLB slots when PCMCIA is not being heavily used? Greg. -- These are my opinions not PPIs. |