Re: [linuxsh-dev] Caches question

[Stuart M. <Stu...@st...>]

On Jun 24, 11:01am, gn...@ch... wrote:
> Subject: Re: [linuxsh-dev] Caches question
> 
> Stuart Menefy wrote:
>  > This also got me thinking about another potential problem. In
>  > update_mmu_cache, the new TLB entry is copied into the TLB using the 
>  > LDTLB instruction. This uses the URC bits of the MMUCR register to
>  > select the TLB entry to replace, so in effect the TLB replaced is
>  > selected at random. If however there is already a TLB entry for this
>  > page, then this could cause two TLB entries to refer to the same page,
>  > and cause a 'Multiple Hit Exception' when the page is next accessed. I
>  > guess the fact that we are not seeing these means that it is not a
>  > problem, but I've not convinced myself that it can never occur.
>  > 
>  > If we have to, it would be pretty easy to fix, effectivly perform
>  > a flush_tlb_page before loading the new entry, but this messy.
> 
> Is there any case where update_mmu_cache is called with valid entry on
> TLB?  As far as I know, there's no such case.

That's what I was hoping, I wasn't sure. If that's the case, good!

Stuart