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[linuxsh-dev] Solution Engin's ATA PC-card enabler
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From: Toshiharu N. <no...@hi...> - 2000-06-07 06:47:06
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I made enabler of the ATA card which I used the PC card
slot on Solution Engine for.
IDE through SuperI/O becomes a storage usable immediately
when I select Solution Engine in Sytem type.
However, I was able to use an ATA card as a storage
because it was not the person who had extension connector.
It works with Solution Engine of SH4.
I want please to hear an opinion of all.
diff -ruN linux-2.4.0-test1/arch/sh/config.in linux-sh/arch/sh/config.in
--- linux-2.4.0-test1/arch/sh/config.in Sun May 21 04:05:29 2000
+++ linux-sh/arch/sh/config.in Wed Jun 7 01:13:01 2000
@@ -61,9 +61,9 @@
bool 'Networking support' CONFIG_NET
-if [ "$CONFIG_SH_SOLUTION_ENGINE" != "y" ]; then
+#if [ "$CONFIG_SH_SOLUTION_ENGINE" != "y" ]; then
bool 'Directly Connected Compact Flash support' CONFIG_CF_ENABLER
-fi
+#fi
bool 'PCI support' CONFIG_PCI
if [ "$CONFIG_PCI" = "y" ]; then
diff -ruN linux-2.4.0-test1/arch/sh/kernel/cf-enabler.c
linux-sh/arch/sh/kernel/cf-enabler.c
--- linux-2.4.0-test1/arch/sh/kernel/cf-enabler.c Mon Mar 6 02:33:55
2000
+++ linux-sh/arch/sh/kernel/cf-enabler.c Wed Jun 7 12:22:14 2000
@@ -12,13 +12,62 @@
#include <asm/io.h>
#include <asm/irq.h>
+#ifdef CONFIG_SH_SOLUTION_ENGINE
+#include <asm/hitachi_se.h>
+/*
+ * 0xB8400000 : Common Memory
+ * 0xB8500000 : Attribute
+ * 0xB8600000 : I/O
+ */
+int __init cf_init(void)
+{
+ if((ctrl_inw(MRSHPC_CSR) & 0x000c) == 0){/* if card detect is true */
+ if((ctrl_inw(MRSHPC_CSR) & 0x0080) == 0){
+ ctrl_outw(0x0674, MRSHPC_CPWCR);/* Card Vcc is 3.3v? */
+ }
+ else{
+ ctrl_outw(0x0678, MRSHPC_CPWCR);/* Card Vcc is 5V */
+ }
+ /*wait(10000);*//* 10ms wait */
+ }
+ else{
+ return 0;
+ }
+/*
+ PC-Card window open
+ flag == COMMON/ATTRIBUTE/IO
+*/
+ /* common window open */
+ ctrl_outw(0x8a84, MRSHPC_MW0CR1);/* window 0xb8400000 */
+ if((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0)
+ ctrl_outw(0x0b00, MRSHPC_MW0CR2);/* common mode & bus width 16bit
SWAP = 1*/
+ else
+ ctrl_outw(0x0300, MRSHPC_MW0CR2);/* common mode & bus width 16bit
SWAP = 0*/
+ /* attribute window open */
+ ctrl_outw(0x8a85, MRSHPC_MW1CR1);/* window 0xb8500000 */
+ if((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0)
+ ctrl_outw(0x0a00, MRSHPC_MW1CR2);/* attribute mode & bus width 16bit
SWAP = 1*/
+ else
+ ctrl_outw(0x0200, MRSHPC_MW1CR2);/* attribute mode & bus width 16bit
SWAP = 0*/
+ /* I/O window open */
+ ctrl_outw(0x8a86, MRSHPC_IOWCR1);/* I/O window 0xb8600000 */
+ ctrl_outw(0x0008, MRSHPC_CDCR); /* I/O card mode */
+ if((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0)
+ ctrl_outw(0x0a00, MRSHPC_IOWCR2);/* bus width 16bit SWAP = 1*/
+ else
+ ctrl_outw(0x0200, MRSHPC_IOWCR2);/* bus width 16bit SWAP = 0*/
+ ctrl_outw(0x2000, MRSHPC_ICR);
+ ctrl_outb(0x00, PA_MRSHPC_MW2 + 0x206);
+ ctrl_outb(0x42, PA_MRSHPC_MW2 + 0x200);
+ return 0;
+}
+#else /* then generic system type */
#define CF_CIS_BASE 0xb8000000
/*
* 0xB8000000 : Attribute
* 0xB8001000 : Common Memory
* 0xBA000000 : I/O
*/
-
int __init cf_init(void)
{
outw(0x0042, CF_CIS_BASE+0x0200);
@@ -26,5 +75,5 @@
disable_irq(14);
return 0;
}
-
+#endif
__initcall (cf_init);
diff -ruN linux-2.4.0-test1/arch/sh/kernel/io_se.c
linux-sh/arch/sh/kernel/io_se.c
--- linux-2.4.0-test1/arch/sh/kernel/io_se.c Mon May 22 12:55:06 2000
+++ linux-sh/arch/sh/kernel/io_se.c Wed Jun 7 12:55:33 2000
@@ -13,15 +13,16 @@
#include <asm/hitachi_se.h>
/* SH pcmcia io window base, start and end. */
-int sh_pcic_io_wbase = 0xb8400000;
-int sh_pcic_io_start;
-int sh_pcic_io_stop;
+int sh_pcic_io_wbase = 0xb8600000;
+int sh_pcic_io_start = 0x3000;
+int sh_pcic_io_stop = 0x3fff;
int sh_pcic_io_type;
int sh_pcic_io_dummy;
static inline void delay(void)
{
ctrl_inw(0xa0000000);
+ ctrl_inw(0xa0000000);
}
/* MS7750 requires special versions of in*, out* routines, since
@@ -31,12 +32,12 @@
static inline volatile __u16 *
port2adr(unsigned int port)
{
- if (port >= 0x2000)
+ if (port >= 0x3000)
+ return (volatile __u16 *) (PA_MRSHPC_IO + (port - 0x3000));
+ else if (port >= 0x2000)
return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000));
else if (port >= 0x1000)
return (volatile __u16 *) (PA_83902 + (port << 1));
- else if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop)
- return (volatile __u16 *) (sh_pcic_io_wbase + (port &~ 1));
else
return (volatile __u16 *) (PA_SUPERIO + (port << 1));
}
@@ -58,9 +59,9 @@
unsigned long inb(unsigned int port)
{
if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop)
- return *(__u8 *) (sh_pcic_io_wbase + 0x40000 + port);
+ return *(__u8 *) port2adr(port);
else if (shifted_port(port))
- return (*port2adr(port) >> 8);
+ return (*port2adr(port) >> 8)&0xff;
else
return (*port2adr(port))&0xff;
}
@@ -70,9 +71,9 @@
unsigned long v;
if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop)
- v = *(__u8 *) (sh_pcic_io_wbase + 0x40000 + port);
+ v = *(__u8 *) port2adr(port);
else if (shifted_port(port))
- v = (*port2adr(port) >> 8);
+ v = (*port2adr(port) >> 8)&0xff;
else
v = (*port2adr(port))&0xff;
delay();
@@ -98,7 +99,7 @@
void outb(unsigned long value, unsigned int port)
{
if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop)
- *(__u8 *)(sh_pcic_io_wbase + port) = value;
+ *(__u8 *)port2adr(port) = (__u8)value;
else if (shifted_port(port))
*(port2adr(port)) = value << 8;
else
@@ -108,7 +109,7 @@
void outb_p(unsigned long value, unsigned int port)
{
if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop)
- *(__u8 *)(sh_pcic_io_wbase + port) = value;
+ *(__u8 *)port2adr(port) = (__u8)value;
else if (shifted_port(port))
*(port2adr(port)) = value << 8;
else
@@ -135,14 +136,14 @@
volatile __u16 *p = port2adr(port);
if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop) {
- volatile __u8 *bp = (__u8 *) (sh_pcic_io_wbase + 0x40000 + port);
+ volatile __u8 *bp = (__u8 *) port2adr(port);
while (count--)
*((__u8 *) addr)++ = *bp;
} else if (shifted_port(port)) {
- while (count--)
- *((__u8 *) addr)++ = *p >> 8;
+ while (count--)
+ *((__u8 *) addr)++ = (*p >> 8)&0xff;
} else {
- while (count--)
+ while (count--)
*((__u8 *) addr)++ = *p;
}
}
@@ -164,14 +165,14 @@
volatile __u16 *p = port2adr(port);
if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop) {
- volatile __u8 *bp = (__u8 *) (sh_pcic_io_wbase + port);
+ volatile __u8 *bp = (__u8 *) port2adr(port);
while (count--)
*bp = *((__u8 *) addr)++;
} else if (shifted_port(port)) {
- while (count--)
+ while (count--)
*p = *((__u8 *) addr)++ << 8;
} else {
- while (count--)
+ while (count--)
*p = *((__u8 *) addr)++;
}
}
@@ -187,7 +188,7 @@
{
maybebadio(outsw, port);
}
-
+
/* Map ISA bus address to the real address. Only for PCMCIA. */
/* ISA page descriptor. */
diff -ruN linux-2.4.0-test1/include/asm-sh/hitachi_se.h
linux-sh/include/asm-sh/hitachi_se.h
--- linux-2.4.0-test1/include/asm-sh/hitachi_se.h Sun May 21 04:05:30
2000
+++ linux-sh/include/asm-sh/hitachi_se.h Wed Jun 7 12:11:43 2000
@@ -39,6 +39,22 @@
#define PA_BCR 0xb1400000 /* FPGA */
#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controler */
+#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */
+#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */
+#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */
+#define MRSHPC_OPTION (PA_MRSHPC + 6)
+#define MRSHPC_CSR (PA_MRSHPC + 8)
+#define MRSHPC_ISR (PA_MRSHPC + 10)
+#define MRSHPC_ICR (PA_MRSHPC + 12)
+#define MRSHPC_CPWCR (PA_MRSHPC + 14)
+#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
+#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
+#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
+#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
+#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
+#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
+#define MRSHPC_CDCR (PA_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
#define BCR_ILCRA (PA_BCR + 0)
#define BCR_ILCRB (PA_BCR + 2)
--
// Toshiharu Nozawa <no...@hi...> //
// HITACHI ULSI Systems Application Engneering Dept.//
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