[linuxsh-cvs] CVS: linux/include/asm-sh processor.h, 1.41, 1.42 cpu-features.h, 1.2, 1.3

[Paul M. <le...@us...>]

Update of /cvsroot/linuxsh/linux/include/asm-sh
In directory sc8-pr-cvs6.sourceforge.net:/tmp/cvs-serv27220/include/asm-sh

Modified Files:
	processor.h cpu-features.h 
Log Message:
Support for optional L2 cache on newer SH-4A CPUs.



Index: processor.h
===================================================================
RCS file: /cvsroot/linuxsh/linux/include/asm-sh/processor.h,v
retrieving revision 1.41
retrieving revision 1.42
diff -u -d -r1.41 -r1.42
--- processor.h	9 Aug 2006 03:53:04 -0000	1.41
+++ processor.h	10 Aug 2006 09:58:50 -0000	1.42
@@ -54,14 +54,15 @@
 };
 
 struct sh_cpuinfo {
-	enum cpu_type type;
+	unsigned int type;
 	unsigned long loops_per_jiffy;
 
-	struct cache_info icache;
-	struct cache_info dcache;
+	struct cache_info icache;	/* Primary I-cache */
+	struct cache_info dcache;	/* Primary D-cache */
+	struct cache_info scache;	/* Secondary cache */
 
 	unsigned long flags;
-};
+} __attribute__ ((aligned(SMP_CACHE_BYTES)));
 
 extern struct sh_cpuinfo boot_cpu_data;
 

Index: cpu-features.h
===================================================================
RCS file: /cvsroot/linuxsh/linux/include/asm-sh/cpu-features.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- cpu-features.h	9 Aug 2006 04:23:26 -0000	1.2
+++ cpu-features.h	10 Aug 2006 09:58:50 -0000	1.3
@@ -19,5 +19,6 @@
 #define CPU_HAS_PERF_COUNTER	0x0010	/* Hardware performance counters */
 #define CPU_HAS_PTEA		0x0020	/* PTEA register */
 #define CPU_HAS_LLSC		0x0040	/* movli.l/movco.l */
+#define CPU_HAS_L2_CACHE	0x0080	/* Secondary cache / URAM */
 
 #endif /* __ASM_SH_CPU_FEATURES_H */