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From: Paul M. <le...@us...> - 2006-08-07 07:50:20
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Update of /cvsroot/linuxsh/linux/drivers/serial In directory sc8-pr-cvs6.sourceforge.net:/tmp/cvs-serv6669/drivers/serial Modified Files: sh-sci.c sh-sci.h Log Message: Add support for SH7710 CPU subtype. Index: sh-sci.c =================================================================== RCS file: /cvsroot/linuxsh/linux/drivers/serial/sh-sci.c,v retrieving revision 1.48 retrieving revision 1.49 diff -u -d -r1.48 -r1.49 --- sh-sci.c 2 Aug 2006 14:40:09 -0000 1.48 +++ sh-sci.c 7 Aug 2006 07:50:16 -0000 1.49 @@ -286,7 +286,7 @@ #endif #if defined(SCIF_ONLY) || defined(SCI_AND_SCIF) -#if defined(CONFIG_CPU_SUBTYPE_SH7300) +#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7710) /* SH7300 doesn't use RTS/CTS */ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) { Index: sh-sci.h =================================================================== RCS file: /cvsroot/linuxsh/linux/drivers/serial/sh-sci.h,v retrieving revision 1.24 retrieving revision 1.25 diff -u -d -r1.24 -r1.25 --- sh-sci.h 2 Aug 2006 14:40:09 -0000 1.24 +++ sh-sci.h 7 Aug 2006 07:50:16 -0000 1.25 @@ -74,6 +74,10 @@ # define SCPDR 0xA4050136 /* 16 bit SCIF */ # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ # define SCIF_ONLY +#elif defined(CONFIG_CPU_SUBTYPE_SH7710) +# define SCSPTR0 0xA4400000 /* 16 bit SCIF */ +# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ +# define SCIF_ONLY #elif defined(CONFIG_CPU_SUBTYPE_SH73180) # define SCPDR 0xA4050138 /* 16 bit SCIF */ # define SCSPTR2 SCPDR @@ -302,7 +306,9 @@ } #ifdef CONFIG_CPU_SH3 -#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) +#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \ + defined(CONFIG_CPU_SUBTYPE_SH7705) || \ + defined(CONFIG_CPU_SUBTYPE_SH7710) #define SCIF_FNS(name, scif_offset, scif_size) \ CPU_SCIF_FNS(name, scif_offset, scif_size) #else @@ -328,7 +334,9 @@ CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) #endif -#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) +#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \ + defined(CONFIG_CPU_SUBTYPE_SH7705) || \ + defined(CONFIG_CPU_SUBTYPE_SH7710) SCIF_FNS(SCSMR, 0x00, 16) SCIF_FNS(SCBRR, 0x04, 8) SCIF_FNS(SCSCR, 0x08, 16) @@ -435,6 +443,13 @@ return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ return 1; } +#elif defined(CONFIG_CPU_SUBTYPE_SH7710) +static inline int sci_rxd_in(struct uart_port *port) +{ + if (port->mapbase == SCSPTR0) + return ctrl_inw(SCSPTR0 + 0x10) & 0x01 ? 1 : 0; + return 1; +} #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ defined(CONFIG_CPU_SUBTYPE_SH7751) || \ defined(CONFIG_CPU_SUBTYPE_SH4_202) @@ -555,4 +570,3 @@ #else /* Generic SH */ #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) #endif - |