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[linuxsh-cvs] CVS: linux/drivers/serial sh-sci.c, 1.44, 1.45 sh-sci.h, 1.21, 1.22
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From: Paul M. <le...@us...> - 2006-08-01 02:13:12
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Update of /cvsroot/linuxsh/linux/drivers/serial In directory sc8-pr-cvs6.sourceforge.net:/tmp/cvs-serv24470/drivers/serial Modified Files: sh-sci.c sh-sci.h Log Message: Rewrite sh-sci for the driver model. All CPU subtypes are required to register a platform device with their port list defined (see the 7780 setup code as an example). Index: sh-sci.c =================================================================== RCS file: /cvsroot/linuxsh/linux/drivers/serial/sh-sci.c,v retrieving revision 1.44 retrieving revision 1.45 diff -u -d -r1.44 -r1.45 --- sh-sci.c 31 Jul 2006 08:28:45 -0000 1.44 +++ sh-sci.c 1 Aug 2006 02:13:08 -0000 1.45 @@ -23,8 +23,6 @@ #include <linux/config.h> #include <linux/module.h> #include <linux/errno.h> -#include <linux/signal.h> -#include <linux/sched.h> #include <linux/timer.h> #include <linux/interrupt.h> #include <linux/tty.h> @@ -33,39 +31,56 @@ #include <linux/major.h> #include <linux/string.h> #include <linux/sysrq.h> -#include <linux/fcntl.h> -#include <linux/ptrace.h> #include <linux/ioport.h> #include <linux/mm.h> -#include <linux/slab.h> #include <linux/init.h> #include <linux/delay.h> #include <linux/console.h> -#include <linux/bitops.h> -#include <linux/generic_serial.h> +#include <linux/platform_device.h> #ifdef CONFIG_CPU_FREQ #include <linux/notifier.h> #include <linux/cpufreq.h> #endif -#include <asm/system.h> -#include <asm/io.h> -#include <asm/irq.h> -#include <asm/uaccess.h> - #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64) #include <asm/clock.h> #include <asm/sh_bios.h> #include <asm/kgdb.h> #endif +#include <asm/sci.h> + #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) #define SUPPORT_SYSRQ #endif #include "sh-sci.h" +struct sci_port { + struct uart_port port; + + /* Port type */ + unsigned int type; + + /* Port IRQs: ERI, RXI, TXI, BRI (optional) */ + unsigned int irqs[SCIx_NR_IRQS]; + + /* Port pin configuration */ + void (*init_pins)(struct uart_port *port, + unsigned int cflag); + + /* Port enable callback */ + void (*enable)(struct uart_port *port); + + /* Port disable callback */ + void (*disable)(struct uart_port *port); + + /* Break timer */ + struct timer_list break_timer; + int break_flag; +}; + #ifdef CONFIG_SH_KGDB static struct sci_port *kgdb_sci_port; #endif @@ -77,12 +92,13 @@ /* Function prototypes */ static void sci_stop_tx(struct uart_port *port); -static struct sci_port sci_ports[]; -static struct uart_driver sci_uart_driver; +#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS -#define SCI_NPORTS sci_uart_driver.nr +static struct sci_port sci_ports[SCI_NPORTS]; +static struct uart_driver sci_uart_driver; -#if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB) +#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && \ + defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB) static inline void handle_error(struct uart_port *port) { /* Clear error flags */ @@ -230,8 +246,8 @@ } #endif -#if defined(SCI_ONLY) || defined(SCI_AND_SCIF) -#if defined(__H8300H__) || defined(__H8300S__) +#if defined(SCI_ONLY) || defined(SCI_AND_SCIF) && \ + defined(__H8300H__) || defined(__H8300S__) static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag) { int ch = (port->mapbase - SMR0) >> 3; @@ -247,7 +263,26 @@ /* tx mark output*/ H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx; } +#else +#define sci_init_pins_sci NULL +#endif + +#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) +static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag) +{ + unsigned int fcr_val = 0; + + if (cflag & CRTSCTS) + fcr_val |= SCFCR_MCE; + + sci_out(port, SCFCR, fcr_val); +} +#else +#define sci_init_pins_irda NULL #endif + +#ifdef SCI_ONLY +#define sci_init_pins_scif NULL #endif #if defined(SCIF_ONLY) || defined(SCI_AND_SCIF) @@ -285,18 +320,6 @@ sci_out(port, SCFCR, fcr_val); } - -#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) -static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag) -{ - unsigned int fcr_val = 0; - - if (cflag & CRTSCTS) - fcr_val |= SCFCR_MCE; - - sci_out(port, SCFCR, fcr_val); -} -#endif #else /* For SH7750 */ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) @@ -713,16 +736,16 @@ scr_status = sci_in(port,SCSCR); /* Tx Interrupt */ - if ((ssr_status&0x0020) && (scr_status&0x0080)) + if ((ssr_status & 0x0020) && (scr_status & 0x0080)) sci_tx_interrupt(irq, ptr, regs); /* Rx Interrupt */ - if ((ssr_status&0x0002) && (scr_status&0x0040)) + if ((ssr_status & 0x0002) && (scr_status & 0x0040)) sci_rx_interrupt(irq, ptr, regs); /* Error Interrupt */ - if ((ssr_status&0x0080) && (scr_status&0x0400)) + if ((ssr_status & 0x0080) && (scr_status & 0x0400)) sci_er_interrupt(irq, ptr, regs); /* Break Interrupt */ - if ((ssr_status&0x0010) && (scr_status&0x0200)) + if ((ssr_status & 0x0010) && (scr_status & 0x0200)) sci_br_interrupt(irq, ptr, regs); return IRQ_HANDLED; @@ -733,7 +756,8 @@ * Here we define a transistion notifier so that we can update all of our * ports' baud rate when the peripheral clock changes. */ -static int sci_notifier(struct notifier_block *self, unsigned long phase, void *p) +static int sci_notifier(struct notifier_block *self, + unsigned long phase, void *p) { struct cpufreq_freqs *freqs = p; int i; @@ -760,8 +784,9 @@ clk_put(clk); } - printk("%s: got a postchange notification for cpu %d (old %d, new %d)\n", - __FUNCTION__, freqs->cpu, freqs->old, freqs->new); + printk(KERN_INFO "%s: got a postchange notification " + "for cpu %d (old %d, new %d)\n", + __FUNCTION__, freqs->cpu, freqs->old, freqs->new); } return NOTIFY_OK; @@ -785,8 +810,9 @@ printk(KERN_ERR "sci: Cannot allocate irq.(IRQ=0)\n"); return -ENODEV; } - if (request_irq(port->irqs[0], sci_mpxed_interrupt, SA_INTERRUPT, - "sci", port)) { + + if (request_irq(port->irqs[0], sci_mpxed_interrupt, + SA_INTERRUPT, "sci", port)) { printk(KERN_ERR "sci: Cannot allocate irq.\n"); return -ENODEV; } @@ -794,8 +820,8 @@ for (i = 0; i < ARRAY_SIZE(handlers); i++) { if (!port->irqs[i]) continue; - if (request_irq(port->irqs[i], handlers[i], SA_INTERRUPT, - desc[i], port)) { + if (request_irq(port->irqs[i], handlers[i], + SA_INTERRUPT, desc[i], port)) { printk(KERN_ERR "sci: Cannot allocate irq.\n"); return -ENODEV; } @@ -948,9 +974,8 @@ sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ #if !defined(SCI_ONLY) - if (port->type == PORT_SCIF) { + if (port->type == PORT_SCIF) sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); - } #endif smr_val = sci_in(port, SCSMR) & 3; @@ -1034,11 +1059,23 @@ port->type = s->type; + switch (port->type) { + case PORT_SCI: + s->init_pins = sci_init_pins_sci; + break; + case PORT_SCIF: + s->init_pins = sci_init_pins_scif; + break; + case PORT_IRDA: + s->init_pins = sci_init_pins_irda; + break; + } + #if defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) if (port->mapbase == 0) port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF"); - port->membase = (void *)port->mapbase; + port->membase = (void __iomem *)port->mapbase; #endif } @@ -1074,418 +1111,61 @@ .verify_port = sci_verify_port, }; -static struct sci_port sci_ports[] = { -#if defined(CONFIG_CPU_SUBTYPE_SH7708) - { - .port = { - .membase = (void *)0xfffffe80, - .mapbase = 0xfffffe80, - .iotype = UPIO_MEM, - .irq = 25, - .ops = &sci_uart_ops, - .flags = UPF_BOOT_AUTOCONF, - .line = 0, - }, - .type = PORT_SCI, - .irqs = SCI_IRQS, - }, -#elif defined(CONFIG_CPU_SUBTYPE_SH7705) - { - .port = { - .membase = (void *)SCIF0, - .mapbase = SCIF0, - .iotype = UPIO_MEM, - .irq = 55, - .ops = &sci_uart_ops, - .flags = UPF_BOOT_AUTOCONF, - .line = 0, - }, - .type = PORT_SCIF, - .irqs = SH3_IRDA_IRQS, - .init_pins = sci_init_pins_scif, - }, - { - .port = { - .membase = (void *)SCIF2, - .mapbase = SCIF2, - .iotype = UPIO_MEM, - .irq = 59, - .ops = &sci_uart_ops, - .flags = UPF_BOOT_AUTOCONF, - .line = 1, - }, - .type = PORT_SCIF, - .irqs = SH3_SCIF_IRQS, - .init_pins = sci_init_pins_scif, - } -#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) - { - .port = { - .membase = (void *)0xfffffe80, - .mapbase = 0xfffffe80, - .iotype = UPIO_MEM, - .irq = 25, - .ops = &sci_uart_ops, - .flags = UPF_BOOT_AUTOCONF, - .line = 0, - }, - .type = PORT_SCI, - .irqs = SCI_IRQS, - }, - { - .port = { - .membase = (void *)0xa4000150, - .mapbase = 0xa4000150, - .iotype = UPIO_MEM, - .irq = 59, - .ops = &sci_uart_ops, - .flags = UPF_BOOT_AUTOCONF, - .line = 1, - }, - .type = PORT_SCIF, - .irqs = SH3_SCIF_IRQS, - .init_pins = sci_init_pins_scif, - }, - { - .port = { - .membase = (void *)0xa4000140, - .mapbase = 0xa4000140, - .iotype = UPIO_MEM, - .irq = 55, - .ops = &sci_uart_ops, - .flags = UPF_BOOT_AUTOCONF, - .line = 2, - }, - .type = PORT_IRDA, - .irqs = SH3_IRDA_IRQS, - .init_pins = sci_init_pins_irda, - } -#elif defined(CONFIG_CPU_SUBTYPE_SH7300) - { - .port = { - .membase = (void *)0xA4430000, - .mapbase = 0xA4430000, - .iotype = UPIO_MEM, - .irq = 25, - .ops = &sci_uart_ops, - .flags = UPF_BOOT_AUTOCONF, - .line = 0, - }, - .type = PORT_SCIF, - .irqs = SH7300_SCIF0_IRQS, - .init_pins = sci_init_pins_scif, - }, -#elif defined(CONFIG_CPU_SUBTYPE_SH73180) - { - .port = { - .membase = (void *)0xffe00000, - .mapbase = 0xffe00000, - .iotype = UPIO_MEM, - .irq = 25, - .ops = &sci_uart_ops, - .flags = UPF_BOOT_AUTOCONF, - .line = 0, - }, - .type = PORT_SCIF, - .irqs = SH73180_SCIF_IRQS, - .init_pins = sci_init_pins_scif, - }, -#elif defined(CONFIG_CPU_SUBTYPE_SH4_202) - { - .port = { - .membase = (void *)0xffe80000, - .mapbase = 0xffe80000, - .iotype = UPIO_MEM, - .irq = 43, - .ops = &sci_uart_ops, - .flags = UPF_BOOT_AUTOCONF, - .line = 0, - }, - .type = PORT_SCIF, - .irqs = SH4_SCIF_IRQS, - .init_pins = sci_init_pins_scif, - }, -#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) - { - .port = { - .membase = (void *)0xffe00000, - .mapbase = 0xffe00000, - .iotype = UPIO_MEM, - .irq = 25, - .ops = &sci_uart_ops, - .flags = UPF_BOOT_AUTOCONF, - .line = 0, - }, - .type = PORT_SCI, - .irqs = SCI_IRQS, - }, - { - .port = { - .membase = (void *)0xffe80000, - .mapbase = 0xffe80000, - .iotype = UPIO_MEM, - .irq = 43, - .ops = &sci_uart_ops, - .flags = UPF_BOOT_AUTOCONF, - .line = 1, - }, - .type = PORT_SCIF, - .irqs = SH4_SCIF_IRQS, - .init_pins = sci_init_pins_scif, - }, -#elif defined(CONFIG_CPU_SUBTYPE_SH7760) - { - .port = { - .membase = (void *)0xfe600000, - .mapbase = 0xfe600000, - .iotype = UPIO_MEM, - .irq = 55, - .ops = &sci_uart_ops, - .flags = UPF_BOOT_AUTOCONF, - .line = 0, - }, - .type = PORT_SCIF, - .irqs = SH7760_SCIF0_IRQS, - .init_pins = sci_init_pins_scif, - }, - { - .port = { - .membase = (void *)0xfe610000, - .mapbase = 0xfe610000, - .iotype = UPIO_MEM, - .irq = 75, - .ops = &sci_uart_ops, - .flags = UPF_BOOT_AUTOCONF, - .line = 1, - }, - .type = PORT_SCIF, - .irqs = SH7760_SCIF1_IRQS, - .init_pins = sci_init_pins_scif, - }, - { - .port = { - .membase = (void *)0xfe620000, - .mapbase = 0xfe620000, - .iotype = UPIO_MEM, - .irq = 79, - .ops = &sci_uart_ops, - .flags = UPF_BOOT_AUTOCONF, - .line = 2, - }, - .type = PORT_SCIF, - .irqs = SH7760_SCIF2_IRQS, - .init_pins = sci_init_pins_scif, - }, -#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1) - { - .port = { - .membase = (void *)0xffe00000, - .mapbase = 0xffe00000, - .iotype = UPIO_MEM, - .irq = 26, - .ops = &sci_uart_ops, - .flags = UPF_BOOT_AUTOCONF, - .line = 0, - }, - .type = PORT_SCIF, - .irqs = STB1_SCIF1_IRQS, - .init_pins = sci_init_pins_scif, - }, - { - .port = { - .membase = (void *)0xffe80000, - .mapbase = 0xffe80000, - .iotype = UPIO_MEM, - .irq = 43, - .ops = &sci_uart_ops, - .flags = UPF_BOOT_AUTOCONF, - .line = 1, - }, - .type = PORT_SCIF, - .irqs = SH4_SCIF_IRQS, - .init_pins = sci_init_pins_scif, - }, -#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) - { - .port = { - .iotype = UPIO_MEM, - .irq = 42, - .ops = &sci_uart_ops, - .flags = UPF_BOOT_AUTOCONF, - .line = 0, - }, - .type = PORT_SCIF, - .irqs = SH5_SCIF_IRQS, - .init_pins = sci_init_pins_scif, - }, -#elif defined(CONFIG_H83007) || defined(CONFIG_H83068) - { - .port = { - .membase = (void *)0x00ffffb0, - .mapbase = 0x00ffffb0, - .iotype = UPIO_MEM, - .irq = 54, - .ops = &sci_uart_ops, - .flags = UPF_BOOT_AUTOCONF, - .line = 0, - }, - .type = PORT_SCI, - .irqs = H8300H_SCI_IRQS0, - .init_pins = sci_init_pins_sci, - }, - { - .port = { - .membase = (void *)0x00ffffb8, - .mapbase = 0x00ffffb8, - .iotype = UPIO_MEM, - .irq = 58, - .ops = &sci_uart_ops, - .flags = UPF_BOOT_AUTOCONF, - .line = 1, - }, - .type = PORT_SCI, - .irqs = H8300H_SCI_IRQS1, - .init_pins = sci_init_pins_sci, - }, - { - .port = { - .membase = (void *)0x00ffffc0, - .mapbase = 0x00ffffc0, - .iotype = UPIO_MEM, - .irq = 62, - .ops = &sci_uart_ops, - .flags = UPF_BOOT_AUTOCONF, - .line = 2, - }, - .type = PORT_SCI, - .irqs = H8300H_SCI_IRQS2, - .init_pins = sci_init_pins_sci, - }, -#elif defined(CONFIG_H8S2678) - { - .port = { - .membase = (void *)0x00ffff78, - .mapbase = 0x00ffff78, - .iotype = UPIO_MEM, - .irq = 90, - .ops = &sci_uart_ops, - .flags = UPF_BOOT_AUTOCONF, - .line = 0, - }, - .type = PORT_SCI, - .irqs = H8S_SCI_IRQS0, - .init_pins = sci_init_pins_sci, - .enable = h8300_sci_enable, - .disable = h8300_sci_disable, - }, - { - .port = { - .membase = (void *)0x00ffff80, - .mapbase = 0x00ffff80, - .iotype = UPIO_MEM, - .irq = 94, - .ops = &sci_uart_ops, - .flags = UPF_BOOT_AUTOCONF, - .line = 1, - }, - .type = PORT_SCI, - .irqs = H8S_SCI_IRQS1, - .init_pins = sci_init_pins_sci, - .enable = h8300_sci_enable, - .disable = h8300_sci_disable, - }, - { - .port = { - .membase = (void *)0x00ffff88, - .mapbase = 0x00ffff88, - .iotype = UPIO_MEM, - .irq = 98, - .ops = &sci_uart_ops, - .flags = UPF_BOOT_AUTOCONF, - .line = 2, - }, - .type = PORT_SCI, - .irqs = H8S_SCI_IRQS2, - .init_pins = sci_init_pins_sci, - .enable = h8300_sci_enable, - .disable = h8300_sci_disable, - }, -#elif defined(CONFIG_CPU_SUBTYPE_SH7770) - { - .port = { - .membase = (void *)0xff923000, - .mapbase = 0xff923000, - .iotype = UPIO_MEM, - .irq = 61, - .ops = &sci_uart_ops, - .flags = UPF_BOOT_AUTOCONF, - .line = 0, - }, - .type = PORT_SCIF, - .irqs = SH7770_SCIF0_IRQS, - .init_pins = sci_init_pins_scif, - }, - { - .port = { - .membase = (void *)0xff924000, - .mapbase = 0xff924000, - .iotype = UPIO_MEM, - .irq = 62, - .ops = &sci_uart_ops, - .flags = UPF_BOOT_AUTOCONF, - .line = 1, - }, - .type = PORT_SCIF, - .irqs = SH7770_SCIF1_IRQS, - .init_pins = sci_init_pins_scif, - }, - { - .port = { - .membase = (void *)0xff925000, - .mapbase = 0xff925000, - .iotype = UPIO_MEM, - .irq = 63, - .ops = &sci_uart_ops, - .flags = UPF_BOOT_AUTOCONF, - .line = 2, - }, - .type = PORT_SCIF, - .irqs = SH7770_SCIF2_IRQS, - .init_pins = sci_init_pins_scif, - }, -#elif defined(CONFIG_CPU_SUBTYPE_SH7780) - { - .port = { - .membase = (void *)0xffe00000, - .mapbase = 0xffe00000, - .iotype = UPIO_MEM, - .irq = 43, - .ops = &sci_uart_ops, - .flags = UPF_BOOT_AUTOCONF, - .line = 0, - }, - .type = PORT_SCIF, - .irqs = SH7780_SCIF0_IRQS, - .init_pins = sci_init_pins_scif, - }, - { - .port = { - .membase = (void *)0xffe10000, - .mapbase = 0xffe10000, - .iotype = UPIO_MEM, - .irq = 79, - .ops = &sci_uart_ops, - .flags = UPF_BOOT_AUTOCONF, - .line = 1, - }, - .type = PORT_SCIF, - .irqs = SH7780_SCIF1_IRQS, - .init_pins = sci_init_pins_scif, - }, +static void __init sci_init_ports(void) +{ + static int first = 1; + int i; + + if (!first) + return; + + first = 0; + + for (i = 0; i < SCI_NPORTS; i++) { + sci_ports[i].port.ops = &sci_uart_ops; + sci_ports[i].port.iotype = UPIO_MEM; + sci_ports[i].port.line = i; + sci_ports[i].port.fifosize = 1; + +#if defined(__H8300H__) || defined(__H8300S__) +#ifdef __H8300S__ + sci_ports[i].enable = h8300_sci_enable; + sci_ports[i].disable = h8300_sci_disable; +#endif + sci_ports[i].port.uartclk = CONFIG_CPU_CLOCK; +#elif defined(CONFIG_SUPERH64) + sci_ports[i].port.uartclk = current_cpu_info.module_clock * 16; #else -#error "CPU subtype not defined" + /* + * XXX: We should use a proper SCI/SCIF clock + */ + { + struct clk *clk = clk_get("module_clk"); + sci_ports[i].port.uartclk = clk_get_rate(clk) * 16; + clk_put(clk); + } #endif -}; + + sci_ports[i].break_timer.data = (unsigned long)&sci_ports[i]; + sci_ports[i].break_timer.function = sci_break_timer; + + init_timer(&sci_ports[i].break_timer); + } +} + +int __init early_serial_setup(struct uart_port *port) +{ + if (unlikely(port->line > SCI_NPORTS)) + return -ENODEV; + + sci_init_ports(); + + sci_ports[port->line].port.membase = port->membase; + sci_ports[port->line].port.mapbase = port->mapbase; + sci_ports[port->line].port.type = port->type; + + return 0; +} #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE /* @@ -1507,36 +1187,38 @@ int flow = 'n'; int ret; + /* + * Check whether an invalid uart number has been specified, and + * if so, search for the first available port that does have + * console support. + */ + if (co->index >= SCI_NPORTS) + co->index = 0; + serial_console_port = &sci_ports[co->index]; port = &serial_console_port->port; + + /* + * Also need to check port->type, we don't actually have any + * UPIO_PORT ports, but uart_report_port() handily misreports + * it anyways if we don't have a port available by the time this is + * called. + */ + if (!port->type) + return -ENODEV; + if (!port->membase || !port->mapbase) + return -ENODEV; + + spin_lock_init(&port->lock); + port->type = serial_console_port->type; -#ifdef CONFIG_SUPERH64 - /* This is especially needed on sh64 to remap the SCIF */ - sci_config_port(port, 0); -#endif + if (port->flags & UPF_IOREMAP) + sci_config_port(port, 0); if (serial_console_port->enable) serial_console_port->enable(port); - /* - * We need to set the initial uartclk here, since otherwise it will - * only ever be setup at sci_init() time. - */ -#if defined(__H8300H__) || defined(__H8300S__) - port->uartclk = CONFIG_CPU_CLOCK; -#elif defined(CONFIG_SUPERH64) - port->uartclk = current_cpu_info.module_clock * 16; -#else - /* - * XXX: Use a proper clock for SCI/SCIF - */ - { - struct clk *clk = clk_get("module_clk"); - port->uartclk = clk_get_rate(clk) * 16; - clk_put(clk); - } -#endif if (options) uart_parse_options(options, &baud, &parity, &bits, &flow); @@ -1554,17 +1236,17 @@ .device = uart_console_device, .write = serial_console_write, .setup = serial_console_setup, - .flags = CON_PRINTBUFFER, + .flags = CON_PRINTBUFFER, .index = -1, .data = &sci_uart_driver, }; static int __init sci_console_init(void) { + sci_init_ports(); register_console(&serial_console); return 0; } - console_initcall(sci_console_init); #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ @@ -1599,6 +1281,8 @@ int parity = 'n'; int flow = 'n'; + spin_lock_init(&port->lock); + if (co->index != kgdb_portnum) co->index = kgdb_portnum; @@ -1627,10 +1311,10 @@ /* Register the KGDB console so we get messages (d'oh!) */ static int __init kgdb_console_init(void) { + sci_init_ports(); register_console(&kgdb_console); return 0; } - console_initcall(kgdb_console_init); #endif /* CONFIG_SH_KGDB_CONSOLE */ @@ -1648,64 +1332,131 @@ static struct uart_driver sci_uart_driver = { .owner = THIS_MODULE, .driver_name = "sci", -#ifdef CONFIG_DEVFS_FS - .devfs_name = "ttsc/", -#endif .dev_name = "ttySC", .major = SCI_MAJOR, .minor = SCI_MINOR_START, + .nr = SCI_NPORTS, .cons = SCI_CONSOLE, }; -static int __init sci_init(void) +/* + * Register a set of serial devices attached to a platform device. The + * list is terminated with a zero flags entry, which means we expect + * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need + * remapping (such as sh64) should also set UPF_IOREMAP. + */ +static int __devinit sci_probe(struct platform_device *dev) { - int chan, ret; + struct plat_sci_port *p = dev->dev.platform_data; + int i; - printk("%s", banner); + for (i = 0; p && p->flags != 0 && i < SCI_NPORTS; p++, i++) { + struct sci_port *sciport = &sci_ports[i]; - sci_uart_driver.nr = ARRAY_SIZE(sci_ports); + sciport->port.mapbase = p->mapbase; - ret = uart_register_driver(&sci_uart_driver); - if (ret == 0) { - for (chan = 0; chan < SCI_NPORTS; chan++) { - struct sci_port *sciport = &sci_ports[chan]; + /* + * For the simple (and majority of) cases where we don't need + * to do any remapping, just cast the cookie directly. + */ + if (p->mapbase && !p->membase && !(p->flags & UPF_IOREMAP)) + p->membase = (void __iomem *)p->mapbase; -#if defined(__H8300H__) || defined(__H8300S__) - sciport->port.uartclk = CONFIG_CPU_CLOCK; -#elif defined(CONFIG_SUPERH64) - sciport->port.uartclk = current_cpu_info.module_clock * 16; -#else - /* XXX: We should use a proper SCI/SCIF clock */ - struct clk *clk = clk_get("module_clk"); - sciport->port.uartclk = clk_get_rate(clk) * 16; - clk_put(clk); -#endif - uart_add_one_port(&sci_uart_driver, &sciport->port); - sciport->break_timer.data = (unsigned long)sciport; - sciport->break_timer.function = sci_break_timer; - init_timer(&sciport->break_timer); - } + sciport->port.membase = p->membase; + + sciport->port.irq = p->irqs[SCIx_TXI_IRQ]; + sciport->port.flags = p->flags; + sciport->port.dev = &dev->dev; + + sciport->type = sciport->port.type = p->type; + + memcpy(&sciport->irqs, &p->irqs, sizeof(p->irqs)); + + uart_add_one_port(&sci_uart_driver, &sciport->port); } #ifdef CONFIG_CPU_FREQ cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER); - printk("sci: CPU frequency notifier registered\n"); + dev_info(&dev->dev, "sci: CPU frequency notifier registered\n"); #endif #ifdef CONFIG_SH_STANDARD_BIOS sh_bios_gdb_detach(); #endif - return ret; + return 0; } -static void __exit sci_exit(void) +static int __devexit sci_remove(struct platform_device *dev) { - int chan; + int i; - for (chan = 0; chan < SCI_NPORTS; chan++) - uart_remove_one_port(&sci_uart_driver, &sci_ports[chan].port); + for (i = 0; i < SCI_NPORTS; i++) + uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port); + + return 0; +} + +static int sci_suspend(struct platform_device *dev, pm_message_t state) +{ + int i; + + for (i = 0; i < SCI_NPORTS; i++) { + struct sci_port *p = &sci_ports[i]; + + if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev) + uart_suspend_port(&sci_uart_driver, &p->port); + } + + return 0; +} + +static int sci_resume(struct platform_device *dev) +{ + int i; + + for (i = 0; i < SCI_NPORTS; i++) { + struct sci_port *p = &sci_ports[i]; + + if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev) + uart_resume_port(&sci_uart_driver, &p->port); + } + + return 0; +} + +static struct platform_driver sci_driver = { + .probe = sci_probe, + .remove = __devexit_p(sci_remove), + .suspend = sci_suspend, + .resume = sci_resume, + .driver = { + .name = "sh-sci", + .owner = THIS_MODULE, + }, +}; + +static int __init sci_init(void) +{ + int ret; + + printk(banner); + + sci_init_ports(); + + ret = uart_register_driver(&sci_uart_driver); + if (likely(ret == 0)) { + ret = platform_driver_register(&sci_driver); + if (unlikely(ret)) + uart_unregister_driver(&sci_uart_driver); + } + return ret; +} + +static void __exit sci_exit(void) +{ + platform_driver_unregister(&sci_driver); uart_unregister_driver(&sci_uart_driver); } Index: sh-sci.h =================================================================== RCS file: /cvsroot/linuxsh/linux/drivers/serial/sh-sci.h,v retrieving revision 1.21 retrieving revision 1.22 diff -u -d -r1.21 -r1.22 --- sh-sci.h 8 Feb 2006 12:24:41 -0000 1.21 +++ sh-sci.h 1 Aug 2006 02:13:08 -0000 1.22 @@ -12,6 +12,7 @@ */ #include <linux/config.h> #include <linux/serial_core.h> +#include <asm/io.h> #if defined(__H8300H__) || defined(__H8300S__) #include <asm/gpio.h> @@ -23,11 +24,6 @@ #endif #endif -/* Offsets into the sci_port->irqs array */ -#define SCIx_ERI_IRQ 0 -#define SCIx_RXI_IRQ 1 -#define SCIx_TXI_IRQ 2 - /* ERI, RXI, TXI, BRI */ #define SCI_IRQS { 23, 24, 25, 0 } #define SH3_SCIF_IRQS { 56, 57, 59, 58 } @@ -49,8 +45,6 @@ #define SH7770_SCIF0_IRQS {61, 61, 61, 61 } #define SH7770_SCIF1_IRQS {62, 62, 62, 62 } #define SH7770_SCIF2_IRQS {63, 63, 63, 63 } -#define SH7780_SCIF0_IRQS {40, 41, 43, 42 } -#define SH7780_SCIF1_IRQS {76, 77, 79, 78 } #if defined(CONFIG_CPU_SUBTYPE_SH7708) # define SCSPTR 0xffffff7c /* 8 bit */ @@ -146,7 +140,7 @@ #elif defined(CONFIG_CPU_SUBTYPE_SH7780) # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ # define SCSPTR1 0xffe10024 /* 16 bit SCIF */ -# define SCIF_OPER 0x0001 /* Overrun error bit */ +# define SCIF_ORER 0x0001 /* Overrun error bit */ # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ # define SCIF_ONLY #else @@ -274,17 +268,6 @@ */ #define SCI_EVENT_WRITE_WAKEUP 0 -struct sci_port { - struct uart_port port; - int type; - unsigned char irqs[4]; /* ERI, RXI, TXI, BRI */ - void (*init_pins)(struct uart_port *port, unsigned int cflag); - void (*enable)(struct uart_port *port); - void (*disable)(struct uart_port *port); - int break_flag; - struct timer_list break_timer; -}; - #define SCI_IN(size, offset) \ unsigned int addr = port->mapbase + (offset); \ if ((size) == 8) { \ |
