[PATCH / HP6XX] : Add Timer values into HD64461.h

[Kristoffer E. <kri...@gm...>]

Greetings,

Shortlog:
This patch adds HD64461 Timer adresses & registers to the HD64461 header file (/include/asm-sh/hd64461.h).
The timers (TMU0 & TMU1) can hold 16bit values and auto loads the counter constant when it
reaches zero. Upon reaching zero it generates an interrupt.

Signed-off-by: Kristoffer Ericson <kri...@gm...>

diff --git a/include/asm-sh/hd64461.h b/include/asm-sh/hd64461.h
index 342ca55..52fcb7e 100644
--- a/include/asm-sh/hd64461.h
+++ b/include/asm-sh/hd64461.h
@@ -225,9 +225,34 @@
 #define	HD64461_NIRR		(CONFIG_HD64461_IOBASE + 0x5000)
 #define	HD64461_NIMR		(CONFIG_HD64461_IOBASE + 0x5002)
 
-#define	HD64461_IRQBASE		OFFCHIP_IRQ_BASE
-#define	OFFCHIP_IRQ_BASE	64
-#define	HD64461_IRQ_NUM		16
+/* Timer control adresses */
+#define	HD64461_TMU_TCVR1	(CONFIG_HD64461_IOBASE + 0x6000)	/* Timer 1 Constant value register */
+#define	HD64461_TMU_TCVR0	(CONFIG_HD64461_IOBASE + 0x6002)	/* Timer 0 Constant value register */
+#define	HD64461_TMU_TRVR1	(CONFIG_HD64461_IOBASE + 0x6004)	/* Timer 1 Read value register */
+#define	HD64461_TMU_TRVR0	(CONFIG_HD64461_IOBASE + 0x6006)	/* Timer 0 Read value register */
+#define	HD64461_TMU_TCR1	(CONFIG_HD64461_IOBASE + 0x6008)	/* Timer 1 Control register */
+#define	HD64461_TMU_TCR0	(CONFIG_HD64461_IOBASE + 0x600a)	/* Timer 0 Control register */
+#define	HD64461_TMU_TIRR	(CONFIG_HD64461_IOBASE + 0x600c)	/* Timer interrupt request register */
+#define	HD64461_TMU_TER		(CONFIG_HD64461_IOBASE + 0x600e)	/* Timer interrupt enable register */
+
+/* Timer Control Register */
+#define	HD64461_TMU_TCR_ENA	0x08	/* Enable timer output TM0x */
+#define	HD64461_TMU_TCR_SCL1	0x06	/* CKIO */	/* remember that CKIO / 16 = inverted 0x06 */
+#define	HD64461_TMU_TCR_SCL4	0x04	/* CKIO / 4 */
+#define	HD64461_TMU_TCR_SCL8	0x02	/* CKIO / 8 */
+#define	HD64461_TMU_TCR_STRT	0x01	/* start counting TM0x */
+
+/* Timer Interrupt Request Register */
+#define	HD64461_TMU_TIRR_TMU1	0x02	/* Interrupt request from Timer 1 */
+#define	HD64461_TMU_TIRR_TMU0	0x01	/* Interrupt request from Timer 0 */
+
+/* Timer Interrupt Enable Register */
+#define	HD64461_TMU_TIMR_TMU1	0x02	/* Interrupt request from Timer 1 is masked */
+#define	HD64461_TMU_TIMR_TMU0	0x01	/* Interrupt request from Timer 0 is masked */
+
+#define	HD64461_IRQBASE		OFFCHIP_IRQ_BASE	/* After here we can set HD64461 interrupts */
+#define	OFFCHIP_IRQ_BASE	64			/* SuperH 7709 Interrupts */
+#define	HD64461_IRQ_NUM		16			/* Number of HD64461 Interrupts */
 
 #define	HD64461_IRQ_UART	(HD64461_IRQBASE+5)
 #define	HD64461_IRQ_IRDA	(HD64461_IRQBASE+6)