SH4 P1/P2 cache/no cache etc - what difference might they make

[Adrian M. <ad...@ne...>]

I am continuing to work on the maple bus driver for the Dreamcast - the
issues are fundamentally about stability.

The old driver took a 1024 byte statically allocated block and applied
P2SEGADDR to it.

I am now using the slab allocator and I was getting a lot of "unaligned
fix up" errors, though when I removed that, and just used the allocated
P1 address the code appears, empirically and on first blush, to be more
stable.

Is that likely? Any reason - bad toolchain? - or am I likely to just not
to have tested the cases enough?