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[PATCH 2/5] SH7720: SH7720 CPU support
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From: Markus B. <sup...@go...> - 2007-08-17 22:36:02
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Hi, The ifdef in sh-sci.h around "#include asm/gpio.h" was removed, because every arch has now this header. On SH7720 the addresses for the PFC get included here. Because there was no reply to my patch extracting the bitpositions for the clocks into a dedicated file and have a generic colck-sh3.c, I used clock-sh7710.c for the sh7720. http://marc.info/?l=linuxsh-dev&m=118661270309548&w=2 Both CPUs have the same clock layout, however the sh7710 clock module is a bit confusing. The bitmasks are 3 bit wide, but the CPU has only 2 bit wide fields. On both CPUs the additional bit is always read as 0, so this is no problem. Early_printk support was added. A init function for sh7720 was added. The scif_sercon_putc could be reused, but the FIFO size got adjusted with an ifdef. Signed-off by: Markus Brunner <sup...@gm...> Signed-off by: Mark Jonas <to...@gm...> --- arch/sh/Kconfig.debug | 1 sh-2.6/arch/sh/drivers/dma/Kconfig | 1 sh-2.6/arch/sh/drivers/dma/dma-sh.c | 12 + sh-2.6/arch/sh/kernel/cpu/sh3/Makefile | 2 sh-2.6/arch/sh/kernel/cpu/sh3/probe.c | 3 sh-2.6/arch/sh/kernel/cpu/sh3/setup-sh7720.c | 211 +++++++++++++++++++++++++++ sh-2.6/arch/sh/kernel/early_printk.c | 38 ++++ sh-2.6/arch/sh/kernel/setup.c | 2 sh-2.6/arch/sh/kernel/timers/timer-tmu.c | 3 sh-2.6/arch/sh/mm/Kconfig | 8 + sh-2.6/drivers/serial/sh-sci.c | 33 ++++ sh-2.6/drivers/serial/sh-sci.h | 33 +++- sh-2.6/include/asm-sh/cpu-sh3/cache.h | 4 sh-2.6/include/asm-sh/cpu-sh3/dma.h | 13 + sh-2.6/include/asm-sh/cpu-sh3/mmu_context.h | 9 - sh-2.6/include/asm-sh/cpu-sh3/timer.h | 9 - sh-2.6/include/asm-sh/cpu-sh3/ubc.h | 3 sh-2.6/include/asm-sh/processor.h | 2 18 files changed, 360 insertions(+), 27 deletions(-) diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/arch/sh/boards/magicpanelr2/Kconfig sh-2.6/arch/sh/boards/magicpanelr2/Kconfig diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/arch/sh/boards/magicpanelr2/Makefile sh-2.6/arch/sh/boards/magicpanelr2/Makefile diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/arch/sh/boards/magicpanelr2/setup.c sh-2.6/arch/sh/boards/magicpanelr2/setup.c diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/arch/sh/drivers/dma/dma-sh.c sh-2.6/arch/sh/drivers/dma/dma-sh.c --- sh-2.6-intc/arch/sh/drivers/dma/dma-sh.c 2007-07-04 21:46:25.000000000 +0200 +++ sh-2.6/arch/sh/drivers/dma/dma-sh.c 2007-08-16 15:49:57.000000000 +0200 @@ -24,13 +24,18 @@ static int dmte_irq_map[] = { DMTE1_IRQ, DMTE2_IRQ, DMTE3_IRQ, -#if defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ +#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ + defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ defined(CONFIG_CPU_SUBTYPE_SH7760) || \ defined(CONFIG_CPU_SUBTYPE_SH7780) DMTE4_IRQ, DMTE5_IRQ, +#endif +#if defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ + defined(CONFIG_CPU_SUBTYPE_SH7760) || \ + defined(CONFIG_CPU_SUBTYPE_SH7780) DMTE6_IRQ, - DMTE7_IRQ, + DMTE7_IRQ, #endif }; @@ -196,7 +201,8 @@ static int sh_dmac_get_dma_residue(struc return ctrl_inl(DMATCR[chan->chan]) << calc_xmit_shift(chan); } -#ifdef CONFIG_CPU_SUBTYPE_SH7780 +#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ + defined(CONFIG_CPU_SUBTYPE_SH7780) #define dmaor_read_reg() ctrl_inw(DMAOR) #define dmaor_write_reg(data) ctrl_outw(data, DMAOR) #else diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/arch/sh/drivers/dma/Kconfig sh-2.6/arch/sh/drivers/dma/Kconfig --- sh-2.6-intc/arch/sh/drivers/dma/Kconfig 2007-07-31 12:11:46.000000000 +0200 +++ sh-2.6/arch/sh/drivers/dma/Kconfig 2007-08-03 09:36:45.000000000 +0200 @@ -12,6 +12,7 @@ config SH_DMA config NR_ONCHIP_DMA_CHANNELS int depends on SH_DMA + default "6" if CPU_SUBTYPE_SH7720 default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R default "12" if CPU_SUBTYPE_SH7780 default "4" diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/arch/sh/drivers/heartbeat.c sh-2.6/arch/sh/drivers/heartbeat.c diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/arch/sh/Kconfig sh-2.6/arch/sh/Kconfig diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/arch/sh/Kconfig.debug sh-2.6/arch/sh/Kconfig.debug --- sh-2.6-intc/arch/sh/Kconfig.debug 2007-08-08 22:59:29.000000000 +0200 +++ sh-2.6/arch/sh/Kconfig.debug 2007-08-16 16:15:07.000000000 +0200 @@ -34,6 +34,7 @@ config EARLY_SCIF_CONSOLE_PORT default "0xfffe9800" if CPU_SUBTYPE_SH7206 default "0xf8420000" if CPU_SUBTYPE_SH7619 default "0xa4400000" if CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7705 + default "0xa4430000" if CPU_SUBTYPE_SH7720 default "0xffc30000" if CPU_SUBTYPE_SHX3 default "0xffe80000" if CPU_SH4 default "0x00000000" diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/arch/sh/kernel/cpu/sh3/Makefile sh-2.6/arch/sh/kernel/cpu/sh3/Makefile --- sh-2.6-intc/arch/sh/kernel/cpu/sh3/Makefile 2007-07-31 12:11:46.000000000 +0200 +++ sh-2.6/arch/sh/kernel/cpu/sh3/Makefile 2007-08-16 17:02:16.000000000 +0200 @@ -12,6 +12,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7708) += setu obj-$(CONFIG_CPU_SUBTYPE_SH7709) += setup-sh770x.o obj-$(CONFIG_CPU_SUBTYPE_SH7710) += setup-sh7710.o obj-$(CONFIG_CPU_SUBTYPE_SH7712) += setup-sh7710.o +obj-$(CONFIG_CPU_SUBTYPE_SH7720) += setup-sh7720.o # Primary on-chip clocks (common) clock-$(CONFIG_CPU_SH3) := clock-sh3.o @@ -19,5 +20,6 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7705) := cl clock-$(CONFIG_CPU_SUBTYPE_SH7706) := clock-sh7706.o clock-$(CONFIG_CPU_SUBTYPE_SH7709) := clock-sh7709.o clock-$(CONFIG_CPU_SUBTYPE_SH7710) := clock-sh7710.o +clock-$(CONFIG_CPU_SUBTYPE_SH7720) := clock-sh7710.o obj-y += $(clock-y) diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/arch/sh/kernel/cpu/sh3/probe.c sh-2.6/arch/sh/kernel/cpu/sh3/probe.c --- sh-2.6-intc/arch/sh/kernel/cpu/sh3/probe.c 2007-07-04 21:46:25.000000000 +0200 +++ sh-2.6/arch/sh/kernel/cpu/sh3/probe.c 2007-08-03 09:33:54.000000000 +0200 @@ -81,6 +81,9 @@ int __init detect_cpu_and_cache_system(v #if defined(CONFIG_CPU_SUBTYPE_SH7712) current_cpu_data.type = CPU_SH7712; #endif +#if defined(CONFIG_CPU_SUBTYPE_SH7720) + current_cpu_data.type = CPU_SH7720; +#endif #if defined(CONFIG_CPU_SUBTYPE_SH7705) current_cpu_data.type = CPU_SH7705; diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/arch/sh/kernel/cpu/sh3/setup-sh7720.c sh-2.6/arch/sh/kernel/cpu/sh3/setup-sh7720.c --- sh-2.6-intc/arch/sh/kernel/cpu/sh3/setup-sh7720.c 1970-01-01 01:00:00.000000000 +0100 +++ sh-2.6/arch/sh/kernel/cpu/sh3/setup-sh7720.c 2007-08-16 17:35:56.000000000 +0200 @@ -0,0 +1,211 @@ +/* + * SH7720 Setup + * + * Copyright (C) 2007 Markus Brunner, Mark Jonas + * + * Based on arch/sh/kernel/cpu/sh4/setup-sh7750.c: + * + * Copyright (C) 2006 Paul Mundt + * Copyright (C) 2006 Jamie Lenehan + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/platform_device.h> +#include <linux/init.h> +#include <linux/serial.h> +#include <linux/io.h> +#include <asm/sci.h> +#include <asm/rtc.h> + +#define INTC_ICR1 0xA4140010UL +#define INTC_ICR_IRLM 0x4000 +#define INTC_ICR_IRQ (~INTC_ICR_IRLM) + +static struct resource rtc_resources[] = { + [0] = { + .start = 0xa413fec0, + .end = 0xa413fec0 + 0x28 - 1, + .flags = IORESOURCE_IO, + }, + [1] = { + /* Period IRQ */ + .start = 21, + .flags = IORESOURCE_IRQ, + }, + [2] = { + /* Carry IRQ */ + .start = 22, + .flags = IORESOURCE_IRQ, + }, + [3] = { + /* Alarm IRQ */ + .start = 20, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_rtc_platform_info rtc_info = { + .capabilities = RTC_CAP_4_DIGIT_YEAR, +}; + +static struct platform_device rtc_device = { + .name = "sh-rtc", + .id = -1, + .num_resources = ARRAY_SIZE(rtc_resources), + .resource = rtc_resources, + .dev = { + .platform_data = &rtc_info, + }, +}; + +static struct plat_sci_port sci_platform_data[] = { + { + .mapbase = 0xa4430000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 80, 80, 80, 80 }, + }, { + .mapbase = 0xa4438000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 81, 81, 81, 81 }, + }, { + + .flags = 0, + } +}; + +static struct platform_device sci_device = { + .name = "sh-sci", + .id = -1, + .dev = { + .platform_data = sci_platform_data, + }, +}; + +static struct platform_device *sh7720_devices[] __initdata = { + &rtc_device, + &sci_device, +}; + +static int __init sh7720_devices_setup(void) +{ + return platform_add_devices(sh7720_devices, + ARRAY_SIZE(sh7720_devices)); +} +__initcall(sh7720_devices_setup); + +enum { + UNUSED = 0, + + /* interrupt sources */ + TMU0, TMU1, TMU2, RTC_ATI, RTC_PRI, RTC_CUI, + WDT, REF_RCMI, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND, + IRQ0, IRQ1, IRQ2, IRQ3, + USBF_SPD, TMU_SUNI, IRQ5, IRQ4, + DMAC1_DEI0, DMAC1_DEI1, DMAC1_DEI2, DMAC1_DEI3, LCDC, SSL, + ADC, DMAC2_DEI4, DMAC2_DEI5, USBFI0, USBFI1, CMT, + SCIF0, SCIF1, + PINT07, PINT815, TPU0, TPU1, TPU2, TPU3, IIC, + SIOF0, SIOF1, MMCI0, MMCI1, MMCI2, MMCI3, PCC, + USBHI, AFEIF, + H_UDI, + /* interrupt groups */ + TMU, RTC, SIM, DMAC1, USBFI, DMAC2, USB, TPU, MMC, +}; + +static struct intc_vect vectors[] __initdata = { + INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), + INTC_VECT(TMU2, 0x440), INTC_VECT(RTC_ATI, 0x480), + INTC_VECT(RTC_PRI, 0x4a0), INTC_VECT(RTC_CUI, 0x4c0), + INTC_VECT(SIM_ERI, 0x4e0), INTC_VECT(SIM_RXI, 0x500), + INTC_VECT(SIM_TXI, 0x520), INTC_VECT(SIM_TEND, 0x540), + INTC_VECT(WDT, 0x560), INTC_VECT(REF_RCMI, 0x580), + /* H_UDI cannot be masked */ INTC_VECT(TMU_SUNI, 0x6c0), + INTC_VECT(USBF_SPD, 0x6e0), INTC_VECT(DMAC1_DEI0, 0x800), + INTC_VECT(DMAC1_DEI1, 0x820), INTC_VECT(DMAC1_DEI2, 0x840), + INTC_VECT(DMAC1_DEI3, 0x860), INTC_VECT(LCDC, 0x900), + INTC_VECT(SSL, 0x980), INTC_VECT(USBFI0, 0xa20), + INTC_VECT(USBFI1, 0xa40), INTC_VECT(USBHI, 0xa60), + INTC_VECT(DMAC2_DEI4, 0xb80), INTC_VECT(DMAC2_DEI5, 0xba0), + INTC_VECT(ADC, 0xbe0), INTC_VECT(SCIF0, 0xc00), + INTC_VECT(SCIF1, 0xc20), INTC_VECT(PINT07, 0xc80), + INTC_VECT(PINT815, 0xca0), INTC_VECT(SIOF0, 0xd00), + INTC_VECT(SIOF1, 0xd20), INTC_VECT(TPU0, 0xd80), + INTC_VECT(TPU1, 0xda0), INTC_VECT(TPU2, 0xdc0), + INTC_VECT(TPU3, 0xde0), INTC_VECT(IIC, 0xe00), + INTC_VECT(MMCI0, 0xe80), INTC_VECT(MMCI1, 0xea0), + INTC_VECT(MMCI2, 0xec0), INTC_VECT(MMCI3, 0xee0), + INTC_VECT(CMT, 0xf00), INTC_VECT(PCC, 0xf60), + INTC_VECT(AFEIF, 0xfe0), +}; + +static struct intc_group groups[] __initdata = { + INTC_GROUP(TMU, TMU0, TMU1, TMU2), + INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), + INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND), + INTC_GROUP(DMAC1, DMAC1_DEI0, DMAC1_DEI1, DMAC1_DEI2, DMAC1_DEI3), + INTC_GROUP(USBFI, USBFI0, USBFI1), + INTC_GROUP(DMAC2, DMAC2_DEI4, DMAC2_DEI5), + INTC_GROUP(TPU, TPU0, TPU1, TPU2, TPU3), + INTC_GROUP(MMC, MMCI0, MMCI1, MMCI2, MMCI3), +}; + +static struct intc_prio priorities[] __initdata = { + INTC_PRIO(SCIF0, 2), + INTC_PRIO(SCIF1, 2), + INTC_PRIO(DMAC1, 1), + INTC_PRIO(DMAC2, 1), + INTC_PRIO(RTC, 2), + INTC_PRIO(TMU, 2), + INTC_PRIO(TPU, 2), +}; + +static struct intc_prio_reg prio_registers[] __initdata = { + { 0xA414FEE2UL, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, + { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } }, + { 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, + { 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } }, + { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } }, + { 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } }, + { 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } }, + { 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } }, + { 0xA4080006UL, 0, 16, 4, /* IPRI */ { SIOF0, SIOF1, MMC, PCC } }, + { 0xA4080008UL, 0, 16, 4, /* IPRJ */ { 0, USBHI, 0, AFEIF } }, +}; + +static __initdata DECLARE_INTC_DESC(intc_desc, "sh7720", vectors, groups, + priorities, NULL, prio_registers, NULL); + +static struct intc_sense_reg sense_registers[] __initdata = { + { INTC_ICR1, 16, 2, { 0, 0, IRQ5, IRQ4, IRQ3, IRQ2, IRQ1, IRQ0 } }, +}; + +static struct intc_vect vectors_irq[] __initdata = { + INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), + INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), + INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), +}; + +static __initdata DECLARE_INTC_DESC(intc_irq_desc, "sh7720-irq", vectors_irq, + NULL, priorities, NULL, prio_registers, sense_registers); + +void __init plat_irq_setup_pins(int mode) +{ + switch (mode) { + case IRQ_MODE_IRQ: + ctrl_outw(ctrl_inw(INTC_ICR1) & INTC_ICR_IRQ, INTC_ICR1); + register_intc_controller(&intc_irq_desc); + break; + default: + BUG(); + } +} + +void __init plat_irq_setup(void) +{ + register_intc_controller(&intc_desc); +} diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/arch/sh/kernel/early_printk.c sh-2.6/arch/sh/kernel/early_printk.c --- sh-2.6-intc/arch/sh/kernel/early_printk.c 2007-08-08 23:15:53.000000000 +0200 +++ sh-2.6/arch/sh/kernel/early_printk.c 2007-08-17 14:47:40.000000000 +0200 @@ -13,6 +13,7 @@ #include <linux/tty.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/delay.h> #ifdef CONFIG_SH_STANDARD_BIOS #include <asm/sh_bios.h> @@ -62,6 +63,18 @@ static struct console bios_console = { #include <linux/serial_core.h> #include "../../../drivers/serial/sh-sci.h" +#if defined(CONFIG_CPU_SUBTYPE_SH7720) +#define EPK_SCSMR_VALUE 0x000 +#define EPK_SCBRR_VALUE 0x00C +#define EPK_FIFO_SIZE 64 +#define EPK_FIFO_BITS (0x7f00 >> 8) +#else +#define EPK_FIFO_SIZE 16 +#define EPK_FIFO_BITS (0x1f00 >> 8) +#endif + + + static struct uart_port scif_port = { .mapbase = CONFIG_EARLY_SCIF_CONSOLE_PORT, .membase = (char __iomem *)CONFIG_EARLY_SCIF_CONSOLE_PORT, @@ -69,7 +82,7 @@ static struct uart_port scif_port = { static void scif_sercon_putc(int c) { - while (((sci_in(&scif_port, SCFDR) & 0x1f00 >> 8) == 16)) + while (((sci_in(&scif_port, SCFDR) & EPK_FIFO_BITS) >= EPK_FIFO_SIZE)) ; sci_out(&scif_port, SCxTDR, c); @@ -105,7 +118,22 @@ static struct console scif_console = { .index = -1, }; -#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_STANDARD_BIOS) +#if !defined(CONFIG_SH_STANDARD_BIOS) +#if defined(CONFIG_CPU_SUBTYPE_SH7720) +static void scif_sercon_init(char *s) +{ + sci_out(&scif_port, SCSCR, 0x0000 ); /* clear TE and RE */ + sci_out(&scif_port, SCFCR, 0x4006 ); /* reset */ + sci_out(&scif_port, SCSCR, 0x0000 ); /* select internal clock */ + sci_out(&scif_port, SCSMR, EPK_SCSMR_VALUE ); + sci_out(&scif_port, SCBRR, EPK_SCBRR_VALUE ); + + mdelay(1); /* wait 1-bit time */ + + sci_out(&scif_port, SCFCR, 0x0030 ); /* TTRG=b'11 */ + sci_out(&scif_port, SCSCR, 0x0030 ); /* TE, RE */ +} +#elif defined(CONFIG_CPU_SH4) #define DEFAULT_BAUD 115200 /* * Simple SCIF init, primarily aimed at SH7750 and other similar SH-4 @@ -146,7 +174,8 @@ static void scif_sercon_init(char *s) ctrl_outw(0, scif_port.mapbase + 36); ctrl_outw(0x30, scif_port.mapbase + 8); } -#endif /* CONFIG_CPU_SH4 && !CONFIG_SH_STANDARD_BIOS */ +#endif /* defined(CONFIG_CPU_SUBTYPE_SH7720) */ +#endif /* !defined(CONFIG_SH_STANDARD_BIOS) */ #endif /* CONFIG_EARLY_SCIF_CONSOLE */ /* @@ -186,7 +215,8 @@ int __init setup_early_printk(char *buf) if (!strncmp(buf, "serial", 6)) { early_console = &scif_console; -#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_STANDARD_BIOS) +#if (defined(CONFIG_CPU_SH4) || defined(CONFIG_CPU_SUBTYPE_SH7720)) && \ + !defined(CONFIG_SH_STANDARD_BIOS) scif_sercon_init(buf + 6); #endif } diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/arch/sh/kernel/setup.c sh-2.6/arch/sh/kernel/setup.c --- sh-2.6-intc/arch/sh/kernel/setup.c 2007-07-31 12:11:46.000000000 +0200 +++ sh-2.6/arch/sh/kernel/setup.c 2007-08-03 09:33:54.000000000 +0200 @@ -279,7 +279,7 @@ static const char *cpu_name[] = { [CPU_SH7705] = "SH7705", [CPU_SH7706] = "SH7706", [CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708", [CPU_SH7709] = "SH7709", [CPU_SH7710] = "SH7710", - [CPU_SH7712] = "SH7712", + [CPU_SH7712] = "SH7712", [CPU_SH7720] = "SH7720", [CPU_SH7729] = "SH7729", [CPU_SH7750] = "SH7750", [CPU_SH7750S] = "SH7750S", [CPU_SH7750R] = "SH7750R", [CPU_SH7751] = "SH7751", [CPU_SH7751R] = "SH7751R", diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/arch/sh/kernel/timers/timer-tmu.c sh-2.6/arch/sh/kernel/timers/timer-tmu.c --- sh-2.6-intc/arch/sh/kernel/timers/timer-tmu.c 2007-07-31 12:11:46.000000000 +0200 +++ sh-2.6/arch/sh/kernel/timers/timer-tmu.c 2007-08-03 09:41:33.000000000 +0200 @@ -173,7 +173,8 @@ static int tmu_timer_init(void) tmu_timer_stop(); -#if !defined(CONFIG_CPU_SUBTYPE_SH7760) && \ +#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \ + !defined(CONFIG_CPU_SUBTYPE_SH7760) && \ !defined(CONFIG_CPU_SUBTYPE_SH7785) && \ !defined(CONFIG_CPU_SUBTYPE_SHX3) ctrl_outb(TMU_TOCR_INIT, TMU_TOCR); diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/arch/sh/Makefile sh-2.6/arch/sh/Makefile diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/arch/sh/mm/Kconfig sh-2.6/arch/sh/mm/Kconfig --- sh-2.6-intc/arch/sh/mm/Kconfig 2007-08-08 22:59:29.000000000 +0200 +++ sh-2.6/arch/sh/mm/Kconfig 2007-08-16 16:19:53.000000000 +0200 @@ -111,6 +111,14 @@ config CPU_SUBTYPE_SH7712 help Select SH7712 if you have a SH3-DSP SH7712 CPU. +config CPU_SUBTYPE_SH7720 + bool "Support SH7720 processor" + select CPU_SH3 + select CPU_HAS_INTC_IRQ + select CPU_HAS_DSP + help + Select SH7720 if you have a SH3-DSP SH7720 CPU. + # SH-4 Processor Support config CPU_SUBTYPE_SH7750 diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/drivers/mtd/maps/Kconfig sh-2.6/drivers/mtd/maps/Kconfig diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/drivers/mtd/maps/magicpanelr2.c sh-2.6/drivers/mtd/maps/magicpanelr2.c diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/drivers/mtd/maps/Makefile sh-2.6/drivers/mtd/maps/Makefile diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/drivers/net/Kconfig sh-2.6/drivers/net/Kconfig diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/drivers/net/smc911x.c sh-2.6/drivers/net/smc911x.c diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/drivers/net/smc911x.h sh-2.6/drivers/net/smc911x.h diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/drivers/serial/sh-sci.c sh-2.6/drivers/serial/sh-sci.c --- sh-2.6-intc/drivers/serial/sh-sci.c 2007-08-08 22:59:29.000000000 +0200 +++ sh-2.6/drivers/serial/sh-sci.c 2007-08-16 16:01:17.000000000 +0200 @@ -4,6 +4,7 @@ * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) * * Copyright (C) 2002 - 2006 Paul Mundt + * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). * * based off of the old drivers/char/sh-sci.c by: * @@ -301,6 +302,38 @@ static void sci_init_pins_scif(struct ua } sci_out(port, SCFCR, fcr_val); } +#elif defined(CONFIG_CPU_SUBTYPE_SH7720) +static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) +{ + unsigned int fcr_val = 0; + unsigned short data; + + if (cflag & CRTSCTS) { + /* enable RTS/CTS */ + if (port->mapbase == 0xa4430000) { /* SCIF0 */ + /* Clear PTCR bit 9-2; enable all scif pins but sck */ + data = ctrl_inw(PORT_PTCR); + ctrl_outw((data & 0xfc03), PORT_PTCR); + } else if (port->mapbase == 0xa4438000) { /* SCIF1 */ + /* Clear PVCR bit 9-2 */ + data = ctrl_inw(PORT_PVCR); + ctrl_outw((data & 0xfc03), PORT_PVCR); + } + fcr_val |= SCFCR_MCE; + } else { + if (port->mapbase == 0xa4430000) { /* SCIF0 */ + /* Clear PTCR bit 5-2; enable only tx and rx */ + data = ctrl_inw(PORT_PTCR); + ctrl_outw((data & 0xffc3), PORT_PTCR); + } else if (port->mapbase == 0xa4438000) { /* SCIF1 */ + /* Clear PVCR bit 5-2 */ + data = ctrl_inw(PORT_PVCR); + ctrl_outw((data & 0xffc3), PORT_PVCR); + } + } + sci_out(port, SCFCR, fcr_val); +} + #elif defined(CONFIG_CPU_SH3) /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/drivers/serial/sh-sci.h sh-2.6/drivers/serial/sh-sci.h --- sh-2.6-intc/drivers/serial/sh-sci.h 2007-08-08 22:59:29.000000000 +0200 +++ sh-2.6/drivers/serial/sh-sci.h 2007-08-17 13:43:16.000000000 +0200 @@ -10,19 +10,19 @@ * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003). * Modified to support H8/300 Series Yoshinori Sato (Feb 2004). * Removed SH7300 support (Jul 2007). + * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Aug 2007). */ #include <linux/serial_core.h> #include <asm/io.h> -#if defined(__H8300H__) || defined(__H8300S__) #include <asm/gpio.h> + #if defined(CONFIG_H83007) || defined(CONFIG_H83068) #include <asm/regs306x.h> #endif #if defined(CONFIG_H8S2678) #include <asm/regs267x.h> #endif -#endif #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ defined(CONFIG_CPU_SUBTYPE_SH7707) || \ @@ -46,6 +46,10 @@ */ # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 # define SCIF_ONLY +#elif defined(CONFIG_CPU_SUBTYPE_SH7720) +# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ +# define SCIF_ONLY +#define SCIF_ORER 0x0200 /* overrun error bit */ #elif defined(CONFIG_SH_RTS7751R2D) # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ # define SCIF_ORER 0x0001 /* overrun error bit */ @@ -217,7 +221,8 @@ #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ -#if defined(CONFIG_CPU_SUBTYPE_SH7705) +#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ + defined(CONFIG_CPU_SUBTYPE_SH7720) #define SCIF_ORER 0x0200 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) #define SCIF_RFDC_MASK 0x007f @@ -254,7 +259,8 @@ # define SCxSR_FER(port) SCIF_FER # define SCxSR_PER(port) SCIF_PER # define SCxSR_BRK(port) SCIF_BRK -#if defined(CONFIG_CPU_SUBTYPE_SH7705) +#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ + defined(CONFIG_CPU_SUBTYPE_SH7720) # define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc) # define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73) # define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf) @@ -362,7 +368,8 @@ CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size) #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) -#elif defined(CONFIG_CPU_SUBTYPE_SH7705) +#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ + defined(CONFIG_CPU_SUBTYPE_SH7720) #define SCIF_FNS(name, scif_offset, scif_size) \ CPU_SCIF_FNS(name, scif_offset, scif_size) #else @@ -388,7 +395,8 @@ CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) #endif -#if defined(CONFIG_CPU_SUBTYPE_SH7705) +#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ + defined(CONFIG_CPU_SUBTYPE_SH7720) SCIF_FNS(SCSMR, 0x00, 16) SCIF_FNS(SCBRR, 0x04, 8) @@ -510,7 +518,15 @@ static inline void set_sh771x_scif_pfc(s return; } } - +#elif defined(CONFIG_CPU_SUBTYPE_SH7720) +static inline int sci_rxd_in(struct uart_port *port) +{ + if (port->mapbase == 0xa4430000) + return sci_in(port, SCxSR) & 0x0003 ? 1 : 0; + else if (port->mapbase == 0xa4438000) + return sci_in(port, SCxSR) & 0x0003 ? 1 : 0; + return 1; +} #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ defined(CONFIG_CPU_SUBTYPE_SH7751) || \ defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ @@ -692,7 +708,8 @@ static inline int sci_rxd_in(struct uart #if defined(CONFIG_CPU_SUBTYPE_SH7780) || \ defined(CONFIG_CPU_SUBTYPE_SH7785) #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) -#elif defined(CONFIG_CPU_SUBTYPE_SH7705) +#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ + defined(CONFIG_CPU_SUBTYPE_SH7720) #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) #elif defined(__H8300H__) || defined(__H8300S__) #define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1) diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/include/asm-sh/cpu-sh3/cache.h sh-2.6/include/asm-sh/cpu-sh3/cache.h --- sh-2.6-intc/include/asm-sh/cpu-sh3/cache.h 2007-07-04 21:46:47.000000000 +0200 +++ sh-2.6/include/asm-sh/cpu-sh3/cache.h 2007-08-03 09:33:54.000000000 +0200 @@ -26,7 +26,9 @@ #define CCR_CACHE_ENABLE CCR_CACHE_CE #define CCR_CACHE_INVALIDATE CCR_CACHE_CF -#if defined(CONFIG_CPU_SUBTYPE_SH7705) || defined(CONFIG_CPU_SUBTYPE_SH7710) +#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ + defined(CONFIG_CPU_SUBTYPE_SH7710) || \ + defined(CONFIG_CPU_SUBTYPE_SH7720) #define CCR3 0xa40000b4 #define CCR_CACHE_16KB 0x00010000 #define CCR_CACHE_32KB 0x00020000 diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/include/asm-sh/cpu-sh3/dma.h sh-2.6/include/asm-sh/cpu-sh3/dma.h --- sh-2.6-intc/include/asm-sh/cpu-sh3/dma.h 2007-07-04 21:46:47.000000000 +0200 +++ sh-2.6/include/asm-sh/cpu-sh3/dma.h 2007-08-03 09:33:54.000000000 +0200 @@ -1,7 +1,20 @@ #ifndef __ASM_CPU_SH3_DMA_H #define __ASM_CPU_SH3_DMA_H + +#if defined(CONFIG_CPU_SUBTYPE_SH7720) +#define SH_DMAC_BASE 0xa4010020 + +#define DMTE0_IRQ 48 +#define DMTE1_IRQ 49 +#define DMTE2_IRQ 50 +#define DMTE3_IRQ 51 +#define DMTE4_IRQ 76 +#define DMTE5_IRQ 77 + +#else #define SH_DMAC_BASE 0xa4000020 +#endif /* Definitions for the SuperH DMAC */ #define TM_BURST 0x00000020 diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/include/asm-sh/cpu-sh3/mmu_context.h sh-2.6/include/asm-sh/cpu-sh3/mmu_context.h --- sh-2.6-intc/include/asm-sh/cpu-sh3/mmu_context.h 2007-07-31 12:11:57.000000000 +0200 +++ sh-2.6/include/asm-sh/cpu-sh3/mmu_context.h 2007-08-03 10:01:33.000000000 +0200 @@ -27,12 +27,13 @@ #define TRA 0xffffffd0 #define EXPEVT 0xffffffd4 -#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ - defined(CONFIG_CPU_SUBTYPE_SH7709) || \ +#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ defined(CONFIG_CPU_SUBTYPE_SH7706) || \ - defined(CONFIG_CPU_SUBTYPE_SH7705) || \ + defined(CONFIG_CPU_SUBTYPE_SH7707) || \ + defined(CONFIG_CPU_SUBTYPE_SH7709) || \ + defined(CONFIG_CPU_SUBTYPE_SH7710) || \ defined(CONFIG_CPU_SUBTYPE_SH7712) || \ - defined(CONFIG_CPU_SUBTYPE_SH7710) + defined(CONFIG_CPU_SUBTYPE_SH7720) #define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */ #else #define INTEVT 0xffffffd8 diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/include/asm-sh/cpu-sh3/port.h sh-2.6/include/asm-sh/cpu-sh3/port.h diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/include/asm-sh/cpu-sh3/timer.h sh-2.6/include/asm-sh/cpu-sh3/timer.h --- sh-2.6-intc/include/asm-sh/cpu-sh3/timer.h 2007-07-31 12:11:57.000000000 +0200 +++ sh-2.6/include/asm-sh/cpu-sh3/timer.h 2007-08-03 10:05:16.000000000 +0200 @@ -23,11 +23,13 @@ * --------------------------------------------------------------------------- */ -#if !defined(CONFIG_CPU_SUBTYPE_SH7727) +#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \ + !defined(CONFIG_CPU_SUBTYPE_SH7727) #define TMU_TOCR 0xfffffe90 /* Byte access */ #endif -#if defined(CONFIG_CPU_SUBTYPE_SH7710) +#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \ + defined(CONFIG_CPU_SUBTYPE_SH7720) #define TMU_012_TSTR 0xa412fe92 /* Byte access */ #define TMU0_TCOR 0xa412fe94 /* Long access */ @@ -56,7 +58,8 @@ #define TMU2_TCOR 0xfffffeac /* Long access */ #define TMU2_TCNT 0xfffffeb0 /* Long access */ #define TMU2_TCR 0xfffffeb4 /* Word access */ -#if !defined(CONFIG_CPU_SUBTYPE_SH7727) +#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \ + !defined(CONFIG_CPU_SUBTYPE_SH7727) #define TMU2_TCPR2 0xfffffeb8 /* Long access */ #endif #endif diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/include/asm-sh/cpu-sh3/ubc.h sh-2.6/include/asm-sh/cpu-sh3/ubc.h --- sh-2.6-intc/include/asm-sh/cpu-sh3/ubc.h 2007-07-04 21:46:47.000000000 +0200 +++ sh-2.6/include/asm-sh/cpu-sh3/ubc.h 2007-08-17 13:52:40.000000000 +0200 @@ -11,7 +11,8 @@ #ifndef __ASM_CPU_SH3_UBC_H #define __ASM_CPU_SH3_UBC_H -#if defined(CONFIG_CPU_SUBTYPE_SH7710) +#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \ + defined(CONFIG_CPU_SUBTYPE_SH7720) #define UBC_BARA 0xa4ffffb0 #define UBC_BAMRA 0xa4ffffb4 #define UBC_BBRA 0xa4ffffb8 diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/include/asm-sh/gpio.h sh-2.6/include/asm-sh/gpio.h diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/include/asm-sh/magicpanelr2.h sh-2.6/include/asm-sh/magicpanelr2.h diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/include/asm-sh/port.h sh-2.6/include/asm-sh/port.h diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/include/asm-sh/processor.h sh-2.6/include/asm-sh/processor.h --- sh-2.6-intc/include/asm-sh/processor.h 2007-07-31 12:11:57.000000000 +0200 +++ sh-2.6/include/asm-sh/processor.h 2007-08-03 10:06:36.000000000 +0200 @@ -45,7 +45,7 @@ enum cpu_type { CPU_SH7705, CPU_SH7706, CPU_SH7707, CPU_SH7708, CPU_SH7708S, CPU_SH7708R, CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712, - CPU_SH7729, + CPU_SH7720, CPU_SH7729, /* SH-4 types */ CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R, diff -X sh-2.6/Documentation/dontdiff -upNr sh-2.6-intc/include/asm-sh64/gpio.h sh-2.6/include/asm-sh64/gpio.h |
