Re: sh: intc - add support for x3

[Paul M. <le...@li...>]

On Wed, Aug 01, 2007 at 12:24:33PM +0900, Magnus Damm wrote:
> sh: intc - add support for x3
> 
> This patch converts the cpu specific interrupt setup code for x3 from intc2
> to intc. New vectors are also added to match the preliminary information.
> 
I suppose we'll have to hook up the IPI vectors later..

> +	INTC_GROUP(DTU0, DTU0_TEND, DTU0_AE, DTU0_TMISS),
> +	INTC_GROUP(DTU1, DTU1_TEND, DTU1_AE, DTU1_TMISS),
> +	INTC_GROUP(DTU2, DTU1_TEND, DTU2_AE, DTU2_TMISS),
> +	INTC_GROUP(DTU3, DTU1_TEND, DTU3_AE, DTU3_TMISS),

Careful here, you obviously wanted DTU2_TEND and DTU3_TEND. I've got them
fixed up locally, so I'll just merge those bits from my working tree.

Looks like a good start otherwise. The next items for this are probably
going to be IPI vectors, handling the processor IDs as a relative offset
for the mask regs, and then finally the hardware auto-balancing. Also not
that we can't poke at the offline CPUs register space until they've been
released from their reset vector, this might need a bit of thinking for
guarding against CPU hotplug in how INTC chooses to handle things in SMP
mode.

The current assumption from the loader is that the boot CPU is always
CPU#0, but I'd also like to avoid making this assumption in the code in
as many places as possible, in the event where CPU#0 is otherwise
constrained.

I'll queue it up, thanks.