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[PATCH] Add SH7720 CPU support
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From: Markus B. <sup...@go...> - 2007-07-23 07:11:40
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Hello Paul,
this patch adds support for the SH7720 SH3-DSP CPU to 2.6.22.
How are the chances to get it accepted?
Signed-off by: Markus Brunner <sup...@gm...>
Signed-off by: Mark Jonas <to...@gm...>
---
Status of the patch
DMA is untested. Suggestions how to test it are welcome.
UBC is untested. Booting is fine with, or without the "Wakeup UBC on startup" option.
Not surprising, because the bootloader didn't disable it. Suggestions how to test it are welcome.
Is anybody really using it? It looks a little unmaintained.
We removed the UBC_TYPE_SH7729 define in asm-sh/ubc.h, because it is unused, but looks rather important because of all the ifdef CPU_SUBTYPEs.
A small bug was fixed after line 367 rtc-sh.c. The comment already claimed to stop the RTC,
but actually it was not done. This is not necessary for all CPUs, but at least for 7720 and 7705.
Added asm-sh/port.h and asm-sh/cpu-sh3/port.h because the registers of the PFC
are defined all over the place and port.h seemed to be the right place.
The SH7720 has PINT interrupts, but support wasn't added. The reason is that the
existing driver is not flexible enough.
We tried to implement early printk but failed miserably. The scif_sercon_init function was never called.
Any hints?
kgdb is working, but I have problems using ttySC1, however ttySC1 is working fine for other things.
Ethernet NFS performance is pretty bad (about 500 kB/s). I have not done any research on this yet.
arch/sh/drivers/dma/Kconfig | 1
arch/sh/drivers/dma/dma-sh.c | 11 +-
arch/sh/kernel/cpu/sh3/Makefile | 2
arch/sh/kernel/cpu/sh3/clock-sh7720.c | 88 ++++++++++++++++
arch/sh/kernel/cpu/sh3/probe.c | 3
arch/sh/kernel/cpu/sh3/setup-sh7720.c | 183 ++++++++++++++++++++++++++++++++++
arch/sh/kernel/setup.c | 2
arch/sh/kernel/timers/timer-tmu.c | 1
arch/sh/mm/Kconfig | 8 +
drivers/net/Kconfig | 2
drivers/net/smc911x.h | 4
drivers/rtc/rtc-sh.c | 7 -
drivers/serial/sh-sci.c | 33 ++++++
drivers/serial/sh-sci.h | 40 ++++++-
include/asm-sh/cpu-sh3/cache.h | 4
include/asm-sh/cpu-sh3/dma.h | 13 ++
include/asm-sh/cpu-sh3/mmu_context.h | 11 +-
include/asm-sh/cpu-sh3/port.h | 67 ++++++++++++
include/asm-sh/cpu-sh3/timer.h | 10 +
include/asm-sh/cpu-sh3/ubc.h | 2
include/asm-sh/port.h | 22 ++++
include/asm-sh/processor.h | 2
include/asm-sh/ubc.h | 6 -
23 files changed, 492 insertions(+), 30 deletions(-)
diff -upNr linux-2.6.22-rc7-orig/arch/sh/drivers/dma/dma-sh.c linux-2.6.22-rc7-mod-CPU/arch/sh/drivers/dma/dma-sh.c
--- linux-2.6.22-rc7-orig/arch/sh/drivers/dma/dma-sh.c 2007-07-04 10:27:03.000000000 +0200
+++ linux-2.6.22-rc7-mod-CPU/arch/sh/drivers/dma/dma-sh.c 2007-07-20 16:58:21.000000000 +0200
@@ -24,13 +24,18 @@ static int dmte_irq_map[] = {
DMTE1_IRQ,
DMTE2_IRQ,
DMTE3_IRQ,
-#if defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
+#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
defined(CONFIG_CPU_SUBTYPE_SH7760) || \
defined(CONFIG_CPU_SUBTYPE_SH7780)
DMTE4_IRQ,
DMTE5_IRQ,
+#endif
+#if defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7760) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7780)
DMTE6_IRQ,
- DMTE7_IRQ,
+ DMTE7_IRQ,
#endif
};
@@ -196,7 +201,7 @@ static int sh_dmac_get_dma_residue(struc
return ctrl_inl(DMATCR[chan->chan]) << calc_xmit_shift(chan);
}
-#ifdef CONFIG_CPU_SUBTYPE_SH7780
+#if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7780)
#define dmaor_read_reg() ctrl_inw(DMAOR)
#define dmaor_write_reg(data) ctrl_outw(data, DMAOR)
#else
diff -upNr linux-2.6.22-rc7-orig/arch/sh/drivers/dma/Kconfig linux-2.6.22-rc7-mod-CPU/arch/sh/drivers/dma/Kconfig
--- linux-2.6.22-rc7-orig/arch/sh/drivers/dma/Kconfig 2007-07-04 10:31:07.000000000 +0200
+++ linux-2.6.22-rc7-mod-CPU/arch/sh/drivers/dma/Kconfig 2007-07-20 17:36:48.000000000 +0200
@@ -11,6 +11,7 @@ config SH_DMA
config NR_ONCHIP_DMA_CHANNELS
depends on SH_DMA
int "Number of on-chip DMAC channels"
+ default "6" if CPU_SUBTYPE_SH7720
default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R
default "12" if CPU_SUBTYPE_SH7780
default "4"
diff -upNr linux-2.6.22-rc7-orig/arch/sh/kernel/cpu/sh3/clock-sh7720.c linux-2.6.22-rc7-mod-CPU/arch/sh/kernel/cpu/sh3/clock-sh7720.c
--- linux-2.6.22-rc7-orig/arch/sh/kernel/cpu/sh3/clock-sh7720.c 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.22-rc7-mod-CPU/arch/sh/kernel/cpu/sh3/clock-sh7720.c 2007-07-20 17:37:11.000000000 +0200
@@ -0,0 +1,88 @@
+/*
+ * arch/sh/kernel/cpu/sh3/clock-sh7720.c
+ *
+ * SH7720 support for the clock framework
+ *
+ * Copyright (C) 2005 Paul Mundt
+ * Copyright (C) 2007 Markus Brunner, Mark Jonas
+ *
+ * strongly based on arch/sh/kernel/cpu/sh3/clock-sh7705.c
+ *
+ * FRQCR parsing hacked out of arch/sh/kernel/time.c
+ *
+ * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
+ * Copyright (C) 2000 Philipp Rumpf <pr...@tu...>
+ * Copyright (C) 2002, 2003, 2004 Paul Mundt
+ * Copyright (C) 2002 M. R. Brown <mr...@li...>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <asm/clock.h>
+#include <asm/freq.h>
+#include <linux/io.h>
+
+/*
+ * SH7720 uses the same divisors as the generic SH-3 case, it's just the
+ * FRQCR layout that is a bit different..
+ */
+static int stc_multipliers[] = { 1, 2, 3, 4, 6, 1, 1, 1 };
+static int ifc_divisors[] = { 1, 2, 3, 4, 1, 1, 1, 1 };
+static int pfc_divisors[] = { 1, 2, 3, 4, 6, 1, 1, 1 };
+
+static void master_clk_init(struct clk *clk)
+{
+ clk->rate *= pfc_divisors[ctrl_inw(FRQCR) & 0x0007];
+}
+
+static struct clk_ops sh7720_master_clk_ops = {
+ .init = master_clk_init,
+};
+
+static void module_clk_recalc(struct clk *clk)
+{
+ int idx = ctrl_inw(FRQCR) & 0x0007;
+ clk->rate = clk->parent->rate / pfc_divisors[idx];
+}
+
+static struct clk_ops sh7720_module_clk_ops = {
+ .recalc = module_clk_recalc,
+};
+
+static void bus_clk_recalc(struct clk *clk)
+{
+ int idx = (ctrl_inw(FRQCR) & 0x0300) >> 8;
+ clk->rate = clk->parent->rate / stc_multipliers[idx];
+}
+
+static struct clk_ops sh7720_bus_clk_ops = {
+ .recalc = bus_clk_recalc,
+};
+
+static void cpu_clk_recalc(struct clk *clk)
+{
+ int idx = (ctrl_inw(FRQCR) & 0x0030) >> 4;
+ clk->rate = clk->parent->rate / ifc_divisors[idx];
+}
+
+static struct clk_ops sh7720_cpu_clk_ops = {
+ .recalc = cpu_clk_recalc,
+};
+
+static struct clk_ops *sh7720_clk_ops[] = {
+ &sh7720_master_clk_ops,
+ &sh7720_module_clk_ops,
+ &sh7720_bus_clk_ops,
+ &sh7720_cpu_clk_ops,
+};
+
+void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+{
+ if (idx < ARRAY_SIZE(sh7720_clk_ops)) {
+ *ops = sh7720_clk_ops[idx];
+ }
+}
+
diff -upNr linux-2.6.22-rc7-orig/arch/sh/kernel/cpu/sh3/Makefile linux-2.6.22-rc7-mod-CPU/arch/sh/kernel/cpu/sh3/Makefile
--- linux-2.6.22-rc7-orig/arch/sh/kernel/cpu/sh3/Makefile 2007-07-04 10:31:07.000000000 +0200
+++ linux-2.6.22-rc7-mod-CPU/arch/sh/kernel/cpu/sh3/Makefile 2007-07-19 13:26:49.000000000 +0200
@@ -13,6 +13,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7709) += setu
obj-$(CONFIG_CPU_SUBTYPE_SH7300) += setup-sh7300.o
obj-$(CONFIG_CPU_SUBTYPE_SH7710) += setup-sh7710.o
obj-$(CONFIG_CPU_SUBTYPE_SH7712) += setup-sh7710.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7720) += setup-sh7720.o
# Primary on-chip clocks (common)
clock-$(CONFIG_CPU_SH3) := clock-sh3.o
@@ -21,5 +22,6 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7705) := cl
clock-$(CONFIG_CPU_SUBTYPE_SH7706) := clock-sh7706.o
clock-$(CONFIG_CPU_SUBTYPE_SH7709) := clock-sh7709.o
clock-$(CONFIG_CPU_SUBTYPE_SH7710) := clock-sh7300.o
+clock-$(CONFIG_CPU_SUBTYPE_SH7720) := clock-sh7720.o
obj-y += $(clock-y)
diff -upNr linux-2.6.22-rc7-orig/arch/sh/kernel/cpu/sh3/probe.c linux-2.6.22-rc7-mod-CPU/arch/sh/kernel/cpu/sh3/probe.c
--- linux-2.6.22-rc7-orig/arch/sh/kernel/cpu/sh3/probe.c 2007-07-04 10:31:07.000000000 +0200
+++ linux-2.6.22-rc7-mod-CPU/arch/sh/kernel/cpu/sh3/probe.c 2007-07-20 17:37:25.000000000 +0200
@@ -81,6 +81,9 @@ int __init detect_cpu_and_cache_system(v
#if defined(CONFIG_CPU_SUBTYPE_SH7712)
current_cpu_data.type = CPU_SH7712;
#endif
+#if defined(CONFIG_CPU_SUBTYPE_SH7720)
+ current_cpu_data.type = CPU_SH7720;
+#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7705)
current_cpu_data.type = CPU_SH7705;
diff -upNr linux-2.6.22-rc7-orig/arch/sh/kernel/cpu/sh3/setup-sh7720.c linux-2.6.22-rc7-mod-CPU/arch/sh/kernel/cpu/sh3/setup-sh7720.c
--- linux-2.6.22-rc7-orig/arch/sh/kernel/cpu/sh3/setup-sh7720.c 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.22-rc7-mod-CPU/arch/sh/kernel/cpu/sh3/setup-sh7720.c 2007-07-20 17:37:37.000000000 +0200
@@ -0,0 +1,183 @@
+/*
+ * SH7720 Setup
+ *
+ * Copyright (C) 2007 Markus Brunner, Mark Jonas
+ *
+ * Based on arch/sh(kernel/cpu/setup-sh7750.c:
+ *
+ * Copyright (C) 2006 Paul Mundt
+ * Copyright (C) 2006 Jamie Lenehan
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/serial.h>
+#include <linux/io.h>
+#include <asm/sci.h>
+
+static struct resource rtc_resources[] = {
+ [0] = {
+ .start = 0xa413fec0,
+ .end = 0xa413fec0 + 0x28 - 1,
+ .flags = IORESOURCE_IO,
+ },
+ [1] = {
+ /* Period IRQ */
+ .start = 21,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ /* Carry IRQ */
+ .start = 22,
+ .flags = IORESOURCE_IRQ,
+ },
+ [3] = {
+ /* Alarm IRQ */
+ .start = 20,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device rtc_device = {
+ .name = "sh-rtc",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(rtc_resources),
+ .resource = rtc_resources,
+};
+
+static struct plat_sci_port sci_platform_data[] = {
+ {
+ .mapbase = 0xa4430000,
+ .flags = UPF_BOOT_AUTOCONF,
+ .type = PORT_SCIF,
+ .irqs = { 80, 80, 80, 80 },
+ }, {
+ .mapbase = 0xa4438000,
+ .flags = UPF_BOOT_AUTOCONF,
+ .type = PORT_SCIF,
+ .irqs = { 81, 81, 81, 81 },
+ }, {
+
+ .flags = 0,
+ }
+};
+
+static struct platform_device sci_device = {
+ .name = "sh-sci",
+ .id = -1,
+ .dev = {
+ .platform_data = sci_platform_data,
+ },
+};
+
+static struct platform_device *sh7720_devices[] __initdata = {
+ &rtc_device,
+ &sci_device,
+};
+
+static int __init sh7720_devices_setup(void)
+{
+ return platform_add_devices(sh7720_devices,
+ ARRAY_SIZE(sh7720_devices));
+}
+__initcall(sh7720_devices_setup);
+
+static struct ipr_data sh7720_ipr_map[] = {
+ /* IRQ, IPR-idx, shift, priority */
+ /* IPRA */
+ { 16, 0, 12, 2 }, /* TMU0 TUNI0 */
+ { 17, 0, 8, 2 }, /* TMU1 TUNI1 */
+ { 18, 0, 4, 2 }, /* TMU2 TUNI2 */
+ { 20, 0, 0, 2 }, /* RTC ATI */
+ { 21, 0, 0, 2 }, /* RTC PRI */
+ { 22, 0, 0, 2 }, /* RTC CUI */
+
+ /* IPRB */
+ { 27, 1, 12, 2 }, /* WDT ITI */
+ { 28, 1, 8, 2 }, /* REF RCMI*/
+ { 23, 1, 4, 2 }, /* SIM ERI */
+ { 24, 1, 4, 2 }, /* SIM RXI */
+ { 25, 1, 4, 2 }, /* SIM TXI */
+ { 26, 1, 4, 2 }, /* SIM TEND */
+
+ /* IPRC */
+ /* IRQ3..0 are board specific. */
+
+ /* IPRD */
+ { 38, 3, 8, 2 }, /* TMU SUNI */
+ { 39, 3, 12, 7 }, /* USBF SPD */
+ /* IRQ5..4 are board specific. */
+
+ /* IPRE */
+ { 48, 4, 12, 1 }, /* DMAC_1 DEI0 */
+ { 49, 4, 12, 1 }, /* DMAC_1 DEI1 */
+ { 50, 4, 12, 1 }, /* DMAC_1 DEI2 */
+ { 51, 4, 12, 1 }, /* DMAC_1 DEI3 */
+ { 56, 4, 4, 2 }, /* LCD LCDCI */
+ { 60, 4, 0, 2 }, /* SSL SSLI */
+
+ /* IPRF */
+ { 79, 5, 12, 2 }, /* ADC ADCI */
+ { 76, 5, 8, 1 }, /* DMAC_2 DEI4 */
+ { 77, 5, 8, 1 }, /* DMAC_2 DEI5 */
+ { 65, 5, 4, 7 }, /* USBF USBFI0 */
+ { 66, 5, 4, 7 }, /* USBF USBFI1 */
+ {104, 5, 0, 2 }, /* CMT CMI */
+
+ /* IPRG */
+ { 80, 6, 12, 2 }, /* SCIF0 SCIFI0 */
+ { 81, 6, 8, 2 }, /* SCIF1 SCIFI1 */
+
+ /* IPRH */
+ /* PINTA and PINTB are board specific. */
+ { 92, 7, 4, 2 }, /* TPU TPI0 */
+ { 93, 7, 4, 2 }, /* TPU TPI1 */
+ { 94, 7, 4, 2 }, /* TPU TPI2 */
+ { 95, 7, 4, 2 }, /* TPU TPI3 */
+ { 96, 7, 0, 2 }, /* IIC IICI */
+
+ /* IPRI */
+ { 88, 8, 12, 2 }, /* SIOF0 SIOFI0 */
+ { 89, 8, 8, 2 }, /* SIOF1 SIOFI1 */
+ {100, 8, 4, 2 }, /* MMC MMCI0 */
+ {101, 8, 4, 2 }, /* MMC MMCI1 */
+ {102, 8, 4, 2 }, /* MMC MMCI2 */
+ {103, 8, 4, 2 }, /* MMC MMCI3 */
+ {107, 8, 0, 2 }, /* PCC PCCI */
+
+ /* IPRJ */
+ { 67, 9, 8, 6 }, /* USBH USBHI */
+ {111, 9, 0, 2 }, /* AFEIF AFECI */
+};
+
+static unsigned long ipr_offsets[] = {
+ 0xA414FEE2UL, /* 0: IPRA */
+ 0xA414FEE4UL, /* 1: IPRB */
+ 0xA4140016UL, /* 2: IPRC */
+ 0xA4140018UL, /* 3: IPRD */
+ 0xA414001AUL, /* 4: IPRE */
+ 0xA4080000UL, /* 5: IPRF */
+ 0xA4080002UL, /* 6: IPRG */
+ 0xA4080004UL, /* 7: IPRH */
+ 0xA4080006UL, /* 8: IPRI */
+ 0xA4080008UL /* 9: IPRJ */
+};
+
+/* given the IPR index return the address of the IPR register */
+unsigned int map_ipridx_to_addr(int idx)
+{
+ if (idx >= ARRAY_SIZE(ipr_offsets)) {
+ return 0;
+ }
+ return ipr_offsets[idx];
+}
+
+void __init init_IRQ_ipr()
+{
+ make_ipr_irq(sh7720_ipr_map, ARRAY_SIZE(sh7720_ipr_map));
+}
+
diff -upNr linux-2.6.22-rc7-orig/arch/sh/kernel/setup.c linux-2.6.22-rc7-mod-CPU/arch/sh/kernel/setup.c
--- linux-2.6.22-rc7-orig/arch/sh/kernel/setup.c 2007-07-04 10:31:08.000000000 +0200
+++ linux-2.6.22-rc7-mod-CPU/arch/sh/kernel/setup.c 2007-07-17 09:50:54.000000000 +0200
@@ -409,7 +409,7 @@ static const char *cpu_name[] = {
[CPU_SH7705] = "SH7705", [CPU_SH7706] = "SH7706",
[CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708",
[CPU_SH7709] = "SH7709", [CPU_SH7710] = "SH7710",
- [CPU_SH7712] = "SH7712",
+ [CPU_SH7712] = "SH7712", [CPU_SH7720] = "SH7720",
[CPU_SH7729] = "SH7729", [CPU_SH7750] = "SH7750",
[CPU_SH7750S] = "SH7750S", [CPU_SH7750R] = "SH7750R",
[CPU_SH7751] = "SH7751", [CPU_SH7751R] = "SH7751R",
diff -upNr linux-2.6.22-rc7-orig/arch/sh/kernel/timers/timer-tmu.c linux-2.6.22-rc7-mod-CPU/arch/sh/kernel/timers/timer-tmu.c
--- linux-2.6.22-rc7-orig/arch/sh/kernel/timers/timer-tmu.c 2007-07-04 10:31:08.000000000 +0200
+++ linux-2.6.22-rc7-mod-CPU/arch/sh/kernel/timers/timer-tmu.c 2007-07-20 14:00:21.000000000 +0200
@@ -173,6 +173,7 @@ static int tmu_timer_init(void)
tmu_timer_stop();
#if !defined(CONFIG_CPU_SUBTYPE_SH7300) && \
+ !defined(CONFIG_CPU_SUBTYPE_SH7720) && \
!defined(CONFIG_CPU_SUBTYPE_SH7760) && \
!defined(CONFIG_CPU_SUBTYPE_SH7785)
ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
diff -upNr linux-2.6.22-rc7-orig/arch/sh/mm/Kconfig linux-2.6.22-rc7-mod-CPU/arch/sh/mm/Kconfig
--- linux-2.6.22-rc7-orig/arch/sh/mm/Kconfig 2007-07-04 10:31:08.000000000 +0200
+++ linux-2.6.22-rc7-mod-CPU/arch/sh/mm/Kconfig 2007-07-04 10:39:33.000000000 +0200
@@ -113,6 +113,14 @@ config CPU_SUBTYPE_SH7712
help
Select SH7712 if you have a SH3-DSP SH7712 CPU.
+config CPU_SUBTYPE_SH7720
+ bool "Support SH7720 processor"
+ select CPU_SH3
+ select CPU_HAS_IPR_IRQ
+# select CPU_HAS_PINT_IRQ
+ help
+ Select SH7720 if you have a SH3-DSP SH7720 CPU.
+
comment "SH-4 Processor Support"
config CPU_SUBTYPE_SH7750
diff -upNr linux-2.6.22-rc7-orig/drivers/net/Kconfig linux-2.6.22-rc7-mod-CPU/drivers/net/Kconfig
--- linux-2.6.22-rc7-orig/drivers/net/Kconfig 2007-07-04 10:31:20.000000000 +0200
+++ linux-2.6.22-rc7-mod-CPU/drivers/net/Kconfig 2007-07-19 15:47:19.000000000 +0200
@@ -879,7 +879,7 @@ config SMC911X
tristate "SMSC LAN911[5678] support"
select CRC32
select MII
- depends on NET_ETHERNET && ARCH_PXA
+ depends on NET_ETHERNET && ( ARCH_PXA || SUPERH )
help
This is a driver for SMSC's LAN911x series of Ethernet chipsets
including the new LAN9115, LAN9116, LAN9117, and LAN9118.
diff -upNr linux-2.6.22-rc7-orig/drivers/net/smc911x.h linux-2.6.22-rc7-mod-CPU/drivers/net/smc911x.h
--- linux-2.6.22-rc7-orig/drivers/net/smc911x.h 2007-02-04 19:44:54.000000000 +0100
+++ linux-2.6.22-rc7-mod-CPU/drivers/net/smc911x.h 2007-07-20 13:53:07.000000000 +0200
@@ -36,6 +36,10 @@
#define SMC_USE_PXA_DMA 1
#define SMC_USE_16BIT 0
#define SMC_USE_32BIT 1
+#elif CONFIG_SUPERH
+ #define SMC_USE_SH_DMA 0
+ #define SMC_USE_16BIT 0
+ #define SMC_USE_32BIT 1
#endif
diff -upNr linux-2.6.22-rc7-orig/drivers/rtc/rtc-sh.c linux-2.6.22-rc7-mod-CPU/drivers/rtc/rtc-sh.c
--- linux-2.6.22-rc7-orig/drivers/rtc/rtc-sh.c 2007-07-04 10:31:24.000000000 +0200
+++ linux-2.6.22-rc7-mod-CPU/drivers/rtc/rtc-sh.c 2007-07-20 17:55:26.000000000 +0200
@@ -319,7 +319,8 @@ static int sh_rtc_read_time(struct devic
tm->tm_mday = BCD2BIN(readb(rtc->regbase + RDAYCNT));
tm->tm_mon = BCD2BIN(readb(rtc->regbase + RMONCNT)) - 1;
-#if defined(CONFIG_CPU_SH4)
+#if defined(CONFIG_CPU_SH4) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7720)
yr = readw(rtc->regbase + RYRCNT);
yr100 = BCD2BIN(yr >> 8);
yr &= 0xff;
@@ -365,6 +366,7 @@ static int sh_rtc_set_time(struct device
/* Reset pre-scaler & stop RTC */
tmp = readb(rtc->regbase + RCR2);
tmp |= RCR2_RESET;
+ tmp &= ~RCR2_START;
writeb(tmp, rtc->regbase + RCR2);
writeb(BIN2BCD(tm->tm_sec), rtc->regbase + RSECCNT);
@@ -374,7 +376,8 @@ static int sh_rtc_set_time(struct device
writeb(BIN2BCD(tm->tm_mday), rtc->regbase + RDAYCNT);
writeb(BIN2BCD(tm->tm_mon + 1), rtc->regbase + RMONCNT);
-#ifdef CONFIG_CPU_SH3
+#if defined(CONFIG_CPU_SH3) && \
+ !defined(CONFIG_CPU_SUBTYPE_SH7720)
year = tm->tm_year % 100;
writeb(BIN2BCD(year), rtc->regbase + RYRCNT);
#else
diff -upNr linux-2.6.22-rc7-orig/drivers/serial/sh-sci.c linux-2.6.22-rc7-mod-CPU/drivers/serial/sh-sci.c
--- linux-2.6.22-rc7-orig/drivers/serial/sh-sci.c 2007-07-04 10:31:28.000000000 +0200
+++ linux-2.6.22-rc7-mod-CPU/drivers/serial/sh-sci.c 2007-07-20 17:55:58.000000000 +0200
@@ -4,6 +4,7 @@
* SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
*
* Copyright (C) 2002 - 2006 Paul Mundt
+ * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
*
* based off of the old drivers/char/sh-sci.c by:
*
@@ -306,6 +307,38 @@ static void sci_init_pins_scif(struct ua
}
sci_out(port, SCFCR, fcr_val);
}
+#elif defined(CONFIG_CPU_SUBTYPE_SH7720)
+static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
+{
+ unsigned int fcr_val = 0;
+ unsigned short data;
+
+ if (cflag & CRTSCTS) {
+ /* enable RTS/CTS */
+ if (port->mapbase == 0xa4430000) { /* SCIF0 */
+ /* Clear PTCR bit 9-2; enable all scif pins but sck */
+ data = ctrl_inw(PORT_PTCR);
+ ctrl_outw((data & 0xfc03), PORT_PTCR);
+ } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
+ /* Clear PVCR bit 9-2 */
+ data = ctrl_inw(PORT_PVCR);
+ ctrl_outw((data & 0xfc03), PORT_PVCR);
+ }
+ fcr_val |= SCFCR_MCE;
+ } else {
+ if (port->mapbase == 0xa4430000) { /* SCIF0 */
+ /* Clear PTCR bit 5-2; enable only tx and rx */
+ data = ctrl_inw(PORT_PTCR);
+ ctrl_outw((data & 0xffc3), PORT_PTCR);
+ } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
+ /* Clear PVCR bit 5-2 */
+ data = ctrl_inw(PORT_PVCR);
+ ctrl_outw((data & 0xffc3), PORT_PVCR);
+ }
+ }
+ sci_out(port, SCFCR, fcr_val);
+}
+
#elif defined(CONFIG_CPU_SH3)
/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
diff -upNr linux-2.6.22-rc7-orig/drivers/serial/sh-sci.h linux-2.6.22-rc7-mod-CPU/drivers/serial/sh-sci.h
--- linux-2.6.22-rc7-orig/drivers/serial/sh-sci.h 2007-07-04 10:31:28.000000000 +0200
+++ linux-2.6.22-rc7-mod-CPU/drivers/serial/sh-sci.h 2007-07-20 18:02:16.000000000 +0200
@@ -9,6 +9,7 @@
* Modified to support multiple serial ports. Stuart Menefy (May 2000).
* Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
* Modified to support H8/300 Series Yoshinori Sato (Feb 2004).
+ * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
*/
#include <linux/serial_core.h>
#include <asm/io.h>
@@ -23,6 +24,8 @@
#endif
#endif
+#include <asm/port.h>
+
#if defined(CONFIG_CPU_SUBTYPE_SH7708)
# define SCSPTR 0xffffff7c /* 8 bit */
# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
@@ -53,6 +56,12 @@
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
# define SCIF_ONLY
+
+#elif defined(CONFIG_CPU_SUBTYPE_SH7720)
+# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
+# define SCIF_ONLY
+#define SCIF_ORER 0x0200 /* overrun error bit */
+
#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751)
# define SCSPTR1 0xffe0001c /* 8 bit SCI */
# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
@@ -212,7 +221,9 @@
#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
-#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
+#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7705) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7720)
#define SCIF_ORER 0x0200
#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
#define SCIF_RFDC_MASK 0x007f
@@ -241,7 +252,9 @@
# define SCxSR_ERRORS(port) SCIF_ERRORS
# define SCxSR_RDxF(port) SCIF_RDF
# define SCxSR_TDxE(port) SCIF_TDFE
-#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
+#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7705) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7720)
# define SCxSR_ORER(port) SCIF_ORER
#else
# define SCxSR_ORER(port) 0x0000
@@ -249,7 +262,9 @@
# define SCxSR_FER(port) SCIF_FER
# define SCxSR_PER(port) SCIF_PER
# define SCxSR_BRK(port) SCIF_BRK
-#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
+#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7705) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7720)
# define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc)
# define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73)
# define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf)
@@ -358,7 +373,8 @@
#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
#elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \
- defined(CONFIG_CPU_SUBTYPE_SH7705)
+ defined(CONFIG_CPU_SUBTYPE_SH7705) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7720)
#define SCIF_FNS(name, scif_offset, scif_size) \
CPU_SCIF_FNS(name, scif_offset, scif_size)
#else
@@ -385,7 +401,8 @@
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
- defined(CONFIG_CPU_SUBTYPE_SH7705)
+ defined(CONFIG_CPU_SUBTYPE_SH7705) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7720)
SCIF_FNS(SCSMR, 0x00, 16)
SCIF_FNS(SCBRR, 0x04, 8)
@@ -547,6 +564,16 @@ static inline int sci_rxd_in(struct uart
return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */
return 1;
}
+#elif defined(CONFIG_CPU_SUBTYPE_SH7720)
+static inline int sci_rxd_in(struct uart_port *port)
+{
+ if (port->mapbase == 0xa4430000) {
+ return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
+ } else if (port->mapbase == 0xa4438000) {
+ return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
+ }
+ return 1;
+}
#elif defined(CONFIG_CPU_SUBTYPE_SH73180)
static inline int sci_rxd_in(struct uart_port *port)
{
@@ -691,7 +718,8 @@ static inline int sci_rxd_in(struct uart
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
defined(CONFIG_CPU_SUBTYPE_SH7785)
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
-#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
+#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7720)
#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
#elif defined(__H8300H__) || defined(__H8300S__)
#define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
diff -upNr linux-2.6.22-rc7-orig/include/asm-sh/cpu-sh3/cache.h linux-2.6.22-rc7-mod-CPU/include/asm-sh/cpu-sh3/cache.h
--- linux-2.6.22-rc7-orig/include/asm-sh/cpu-sh3/cache.h 2007-02-04 19:44:54.000000000 +0100
+++ linux-2.6.22-rc7-mod-CPU/include/asm-sh/cpu-sh3/cache.h 2007-07-19 15:29:34.000000000 +0200
@@ -26,7 +26,9 @@
#define CCR_CACHE_ENABLE CCR_CACHE_CE
#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
-#if defined(CONFIG_CPU_SUBTYPE_SH7705) || defined(CONFIG_CPU_SUBTYPE_SH7710)
+#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7710) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7720)
#define CCR3 0xa40000b4
#define CCR_CACHE_16KB 0x00010000
#define CCR_CACHE_32KB 0x00020000
diff -upNr linux-2.6.22-rc7-orig/include/asm-sh/cpu-sh3/dma.h linux-2.6.22-rc7-mod-CPU/include/asm-sh/cpu-sh3/dma.h
--- linux-2.6.22-rc7-orig/include/asm-sh/cpu-sh3/dma.h 2007-07-04 10:31:41.000000000 +0200
+++ linux-2.6.22-rc7-mod-CPU/include/asm-sh/cpu-sh3/dma.h 2007-07-18 09:34:25.000000000 +0200
@@ -1,7 +1,20 @@
#ifndef __ASM_CPU_SH3_DMA_H
#define __ASM_CPU_SH3_DMA_H
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7720)
+#define SH_DMAC_BASE 0xa4010020
+
+#define DMTE0_IRQ 48
+#define DMTE1_IRQ 49
+#define DMTE2_IRQ 50
+#define DMTE3_IRQ 51
+#define DMTE4_IRQ 76
+#define DMTE5_IRQ 77
+
+#else
#define SH_DMAC_BASE 0xa4000020
+#endif
/* Definitions for the SuperH DMAC */
#define TM_BURST 0x00000020
diff -upNr linux-2.6.22-rc7-orig/include/asm-sh/cpu-sh3/mmu_context.h linux-2.6.22-rc7-mod-CPU/include/asm-sh/cpu-sh3/mmu_context.h
--- linux-2.6.22-rc7-orig/include/asm-sh/cpu-sh3/mmu_context.h 2007-07-04 10:31:41.000000000 +0200
+++ linux-2.6.22-rc7-mod-CPU/include/asm-sh/cpu-sh3/mmu_context.h 2007-07-20 17:02:17.000000000 +0200
@@ -27,13 +27,14 @@
#define TRA 0xffffffd0
#define EXPEVT 0xffffffd4
-#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
- defined(CONFIG_CPU_SUBTYPE_SH7709) || \
- defined(CONFIG_CPU_SUBTYPE_SH7706) || \
- defined(CONFIG_CPU_SUBTYPE_SH7300) || \
+#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
defined(CONFIG_CPU_SUBTYPE_SH7705) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7706) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7707) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7709) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7710) || \
defined(CONFIG_CPU_SUBTYPE_SH7712) || \
- defined(CONFIG_CPU_SUBTYPE_SH7710)
+ defined(CONFIG_CPU_SUBTYPE_SH7720)
#define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */
#else
#define INTEVT 0xffffffd8
diff -upNr linux-2.6.22-rc7-orig/include/asm-sh/cpu-sh3/port.h linux-2.6.22-rc7-mod-CPU/include/asm-sh/cpu-sh3/port.h
--- linux-2.6.22-rc7-orig/include/asm-sh/cpu-sh3/port.h 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.22-rc7-mod-CPU/include/asm-sh/cpu-sh3/port.h 2007-07-20 12:35:28.000000000 +0200
@@ -0,0 +1,67 @@
+/*
+ * include/asm-sh/cpu-sh3/port.h
+ *
+ * Copyright (C) 2007 Markus Brunner, Mark Jonas
+ *
+ * Addresses for the Pin Function Controller
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef _CPU_SH3_PORT_H
+#define _CPU_SH3_PORT_H
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7720)
+
+/* Control registers */
+#define PORT_PACR 0xA4050100UL
+#define PORT_PBCR 0xA4050102UL
+#define PORT_PCCR 0xA4050104UL
+#define PORT_PDCR 0xA4050106UL
+#define PORT_PECR 0xA4050108UL
+#define PORT_PFCR 0xA405010AUL
+#define PORT_PGCR 0xA405010CUL
+#define PORT_PHCR 0xA405010EUL
+#define PORT_PJCR 0xA4050110UL
+#define PORT_PKCR 0xA4050112UL
+#define PORT_PLCR 0xA4050114UL
+#define PORT_PMCR 0xA4050116UL
+#define PORT_PPCR 0xA4050118UL
+#define PORT_PRCR 0xA405011AUL
+#define PORT_PSCR 0xA405011CUL
+#define PORT_PTCR 0xA405011EUL
+#define PORT_PUCR 0xA4050120UL
+#define PORT_PVCR 0xA4050122UL
+
+/* Data registers */
+#define PORT_PADR 0xA4050140UL
+/* Address of PORT_PBDR is wrong in the datasheet, see errata 2005-09-21 */
+#define PORT_PBDR 0xA4050142UL
+#define PORT_PCDR 0xA4050144UL
+#define PORT_PDDR 0xA4050146UL
+#define PORT_PEDR 0xA4050148UL
+#define PORT_PFDR 0xA405014AUL
+#define PORT_PGDR 0xA405014CUL
+#define PORT_PHDR 0xA405014EUL
+#define PORT_PJDR 0xA4050150UL
+#define PORT_PKDR 0xA4050152UL
+#define PORT_PLDR 0xA4050154UL
+#define PORT_PMDR 0xA4050156UL
+#define PORT_PPDR 0xA4050158UL
+#define PORT_PRDR 0xA405015AUL
+#define PORT_PSDR 0xA405015CUL
+#define PORT_PTDR 0xA405015EUL
+#define PORT_PUDR 0xA4050160UL
+#define PORT_PVDR 0xA4050162UL
+
+/* Pin Select Registers */
+#define PORT_PSELA 0xA4050124UL
+#define PORT_PSELB 0xA4050126UL
+#define PORT_PSELC 0xA4050128UL
+#define PORT_PSELD 0xA405012AUL
+
+#endif
+
+#endif
diff -upNr linux-2.6.22-rc7-orig/include/asm-sh/cpu-sh3/timer.h linux-2.6.22-rc7-mod-CPU/include/asm-sh/cpu-sh3/timer.h
--- linux-2.6.22-rc7-orig/include/asm-sh/cpu-sh3/timer.h 2007-02-04 19:44:54.000000000 +0100
+++ linux-2.6.22-rc7-mod-CPU/include/asm-sh/cpu-sh3/timer.h 2007-07-20 17:38:37.000000000 +0200
@@ -24,11 +24,14 @@
* ---------------------------------------------------------------------------
*/
-#if !defined(CONFIG_CPU_SUBTYPE_SH7727)
+#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \
+ !defined(CONFIG_CPU_SUBTYPE_SH7727)
#define TMU_TOCR 0xfffffe90 /* Byte access */
#endif
-#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7710)
+#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7710) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7720)
#define TMU_TSTR 0xa412fe92 /* Byte access */
#define TMU0_TCOR 0xa412fe94 /* Long access */
@@ -57,7 +60,8 @@
#define TMU2_TCOR 0xfffffeac /* Long access */
#define TMU2_TCNT 0xfffffeb0 /* Long access */
#define TMU2_TCR 0xfffffeb4 /* Word access */
-#if !defined(CONFIG_CPU_SUBTYPE_SH7727)
+#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \
+ !defined(CONFIG_CPU_SUBTYPE_SH7727)
#define TMU2_TCPR2 0xfffffeb8 /* Long access */
#endif
#endif
diff -upNr linux-2.6.22-rc7-orig/include/asm-sh/cpu-sh3/ubc.h linux-2.6.22-rc7-mod-CPU/include/asm-sh/cpu-sh3/ubc.h
--- linux-2.6.22-rc7-orig/include/asm-sh/cpu-sh3/ubc.h 2007-02-04 19:44:54.000000000 +0100
+++ linux-2.6.22-rc7-mod-CPU/include/asm-sh/cpu-sh3/ubc.h 2007-07-20 12:35:28.000000000 +0200
@@ -11,7 +11,7 @@
#ifndef __ASM_CPU_SH3_UBC_H
#define __ASM_CPU_SH3_UBC_H
-#if defined(CONFIG_CPU_SUBTYPE_SH7710)
+#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7720)
#define UBC_BARA 0xa4ffffb0
#define UBC_BAMRA 0xa4ffffb4
#define UBC_BBRA 0xa4ffffb8
diff -upNr linux-2.6.22-rc7-orig/include/asm-sh/port.h linux-2.6.22-rc7-mod-CPU/include/asm-sh/port.h
--- linux-2.6.22-rc7-orig/include/asm-sh/port.h 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.22-rc7-mod-CPU/include/asm-sh/port.h 2007-07-20 12:35:45.000000000 +0200
@@ -0,0 +1,22 @@
+/*
+ * include/asm-sh/port.h
+ *
+ * Copyright (C) 2007 Markus Brunner, Mark Jonas
+ *
+ * Addresses for the Pin Function Controller
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef _ASM_SH_PORT_H
+#define _ASM_SH_PORT_H
+
+#if defined(CONFIG_CPU_SH3)
+
+#include <asm/cpu/port.h>
+
+#endif
+
+#endif
diff -upNr linux-2.6.22-rc7-orig/include/asm-sh/processor.h linux-2.6.22-rc7-mod-CPU/include/asm-sh/processor.h
--- linux-2.6.22-rc7-orig/include/asm-sh/processor.h 2007-07-04 10:31:41.000000000 +0200
+++ linux-2.6.22-rc7-mod-CPU/include/asm-sh/processor.h 2007-07-04 10:39:33.000000000 +0200
@@ -45,7 +45,7 @@ enum cpu_type {
CPU_SH7705, CPU_SH7706, CPU_SH7707,
CPU_SH7708, CPU_SH7708S, CPU_SH7708R,
CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712,
- CPU_SH7729, CPU_SH7300,
+ CPU_SH7720, CPU_SH7729, CPU_SH7300,
/* SH-4 types */
CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,
diff -upNr linux-2.6.22-rc7-orig/include/asm-sh/ubc.h linux-2.6.22-rc7-mod-CPU/include/asm-sh/ubc.h
--- linux-2.6.22-rc7-orig/include/asm-sh/ubc.h 2007-07-04 10:27:25.000000000 +0200
+++ linux-2.6.22-rc7-mod-CPU/include/asm-sh/ubc.h 2007-07-20 12:35:45.000000000 +0200
@@ -15,12 +15,6 @@
#include <asm/cpu/ubc.h>
/* User Break Controller */
-#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
- defined(CONFIG_CPU_SUBTYPE_SH7300)
-#define UBC_TYPE_SH7729 (current_cpu_data.type == CPU_SH7729)
-#else
-#define UBC_TYPE_SH7729 0
-#endif
#define BAMR_ASID (1 << 2)
#define BAMR_NONE 0
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